Lines Matching refs:rs
33 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, in EmitR() argument
35 CHECK_NE(rs, kNoGpuRegister); in EmitR()
39 static_cast<uint32_t>(rs) << kRsShift | in EmitR()
47 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { in EmitI() argument
48 CHECK_NE(rs, kNoGpuRegister); in EmitI()
51 static_cast<uint32_t>(rs) << kRsShift | in EmitI()
57 void Mips64Assembler::EmitI21(int opcode, GpuRegister rs, uint32_t imm21) { in EmitI21() argument
58 CHECK_NE(rs, kNoGpuRegister); in EmitI21()
60 static_cast<uint32_t>(rs) << kRsShift | in EmitI21()
94 void Mips64Assembler::Add(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Add() argument
95 EmitR(0, rs, rt, rd, 0, 0x20); in Add()
98 void Mips64Assembler::Addi(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Addi() argument
99 EmitI(0x8, rs, rt, imm16); in Addi()
102 void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Addu() argument
103 EmitR(0, rs, rt, rd, 0, 0x21); in Addu()
106 void Mips64Assembler::Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Addiu() argument
107 EmitI(0x9, rs, rt, imm16); in Addiu()
110 void Mips64Assembler::Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Daddu() argument
111 EmitR(0, rs, rt, rd, 0, 0x2d); in Daddu()
114 void Mips64Assembler::Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Daddiu() argument
115 EmitI(0x19, rs, rt, imm16); in Daddiu()
118 void Mips64Assembler::Sub(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Sub() argument
119 EmitR(0, rs, rt, rd, 0, 0x22); in Sub()
122 void Mips64Assembler::Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Subu() argument
123 EmitR(0, rs, rt, rd, 0, 0x23); in Subu()
126 void Mips64Assembler::Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dsubu() argument
127 EmitR(0, rs, rt, rd, 0, 0x2f); in Dsubu()
130 void Mips64Assembler::MultR2(GpuRegister rs, GpuRegister rt) { in MultR2() argument
131 EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x18); in MultR2()
134 void Mips64Assembler::MultuR2(GpuRegister rs, GpuRegister rt) { in MultuR2() argument
135 EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x19); in MultuR2()
138 void Mips64Assembler::DivR2(GpuRegister rs, GpuRegister rt) { in DivR2() argument
139 EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x1a); in DivR2()
142 void Mips64Assembler::DivuR2(GpuRegister rs, GpuRegister rt) { in DivuR2() argument
143 EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x1b); in DivuR2()
146 void Mips64Assembler::MulR2(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in MulR2() argument
147 EmitR(0x1c, rs, rt, rd, 0, 2); in MulR2()
150 void Mips64Assembler::DivR2(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in DivR2() argument
151 DivR2(rs, rt); in DivR2()
155 void Mips64Assembler::ModR2(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in ModR2() argument
156 DivR2(rs, rt); in ModR2()
160 void Mips64Assembler::DivuR2(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in DivuR2() argument
161 DivuR2(rs, rt); in DivuR2()
165 void Mips64Assembler::ModuR2(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in ModuR2() argument
166 DivuR2(rs, rt); in ModuR2()
170 void Mips64Assembler::MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in MulR6() argument
171 EmitR(0, rs, rt, rd, 2, 0x18); in MulR6()
174 void Mips64Assembler::DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in DivR6() argument
175 EmitR(0, rs, rt, rd, 2, 0x1a); in DivR6()
178 void Mips64Assembler::ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in ModR6() argument
179 EmitR(0, rs, rt, rd, 3, 0x1a); in ModR6()
182 void Mips64Assembler::DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in DivuR6() argument
183 EmitR(0, rs, rt, rd, 2, 0x1b); in DivuR6()
186 void Mips64Assembler::ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in ModuR6() argument
187 EmitR(0, rs, rt, rd, 3, 0x1b); in ModuR6()
190 void Mips64Assembler::Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dmul() argument
191 EmitR(0, rs, rt, rd, 2, 0x1c); in Dmul()
194 void Mips64Assembler::Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Ddiv() argument
195 EmitR(0, rs, rt, rd, 2, 0x1e); in Ddiv()
198 void Mips64Assembler::Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dmod() argument
199 EmitR(0, rs, rt, rd, 3, 0x1e); in Dmod()
202 void Mips64Assembler::Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Ddivu() argument
203 EmitR(0, rs, rt, rd, 2, 0x1f); in Ddivu()
206 void Mips64Assembler::Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dmodu() argument
207 EmitR(0, rs, rt, rd, 3, 0x1f); in Dmodu()
210 void Mips64Assembler::And(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in And() argument
211 EmitR(0, rs, rt, rd, 0, 0x24); in And()
214 void Mips64Assembler::Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Andi() argument
215 EmitI(0xc, rs, rt, imm16); in Andi()
218 void Mips64Assembler::Or(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Or() argument
219 EmitR(0, rs, rt, rd, 0, 0x25); in Or()
222 void Mips64Assembler::Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Ori() argument
223 EmitI(0xd, rs, rt, imm16); in Ori()
226 void Mips64Assembler::Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Xor() argument
227 EmitR(0, rs, rt, rd, 0, 0x26); in Xor()
230 void Mips64Assembler::Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Xori() argument
231 EmitI(0xe, rs, rt, imm16); in Xori()
234 void Mips64Assembler::Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Nor() argument
235 EmitR(0, rs, rt, rd, 0, 0x27); in Nor()
246 void Mips64Assembler::Dext(GpuRegister rt, GpuRegister rs, int pos, int size_less_one) { in Dext() argument
249 EmitR(0x1f, rs, rt, static_cast<GpuRegister>(size_less_one), pos, 3); in Dext()
264 void Mips64Assembler::Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Sllv() argument
265 EmitR(0, rs, rt, rd, 0, 0x04); in Sllv()
268 void Mips64Assembler::Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Srlv() argument
269 EmitR(0, rs, rt, rd, 0, 0x06); in Srlv()
272 void Mips64Assembler::Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Srav() argument
273 EmitR(0, rs, rt, rd, 0, 0x07); in Srav()
300 void Mips64Assembler::Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Dsllv() argument
301 EmitR(0, rs, rt, rd, 0, 0x14); in Dsllv()
304 void Mips64Assembler::Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Dsrlv() argument
305 EmitR(0, rs, rt, rd, 0, 0x16); in Dsrlv()
308 void Mips64Assembler::Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Dsrav() argument
309 EmitR(0, rs, rt, rd, 0, 0x17); in Dsrav()
312 void Mips64Assembler::Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lb() argument
313 EmitI(0x20, rs, rt, imm16); in Lb()
316 void Mips64Assembler::Lh(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lh() argument
317 EmitI(0x21, rs, rt, imm16); in Lh()
320 void Mips64Assembler::Lw(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lw() argument
321 EmitI(0x23, rs, rt, imm16); in Lw()
324 void Mips64Assembler::Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Ld() argument
325 EmitI(0x37, rs, rt, imm16); in Ld()
328 void Mips64Assembler::Lbu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lbu() argument
329 EmitI(0x24, rs, rt, imm16); in Lbu()
332 void Mips64Assembler::Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lhu() argument
333 EmitI(0x25, rs, rt, imm16); in Lhu()
336 void Mips64Assembler::Lwu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lwu() argument
337 EmitI(0x27, rs, rt, imm16); in Lwu()
344 void Mips64Assembler::Dahi(GpuRegister rs, uint16_t imm16) { in Dahi() argument
345 EmitI(1, rs, static_cast<GpuRegister>(6), imm16); in Dahi()
348 void Mips64Assembler::Dati(GpuRegister rs, uint16_t imm16) { in Dati() argument
349 EmitI(1, rs, static_cast<GpuRegister>(0x1e), imm16); in Dati()
365 void Mips64Assembler::Sb(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sb() argument
366 EmitI(0x28, rs, rt, imm16); in Sb()
369 void Mips64Assembler::Sh(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sh() argument
370 EmitI(0x29, rs, rt, imm16); in Sh()
373 void Mips64Assembler::Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sw() argument
374 EmitI(0x2b, rs, rt, imm16); in Sw()
377 void Mips64Assembler::Sd(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sd() argument
378 EmitI(0x3f, rs, rt, imm16); in Sd()
381 void Mips64Assembler::Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Slt() argument
382 EmitR(0, rs, rt, rd, 0, 0x2a); in Slt()
385 void Mips64Assembler::Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Sltu() argument
386 EmitR(0, rs, rt, rd, 0, 0x2b); in Sltu()
389 void Mips64Assembler::Slti(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Slti() argument
390 EmitI(0xa, rs, rt, imm16); in Slti()
393 void Mips64Assembler::Sltiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sltiu() argument
394 EmitI(0xb, rs, rt, imm16); in Sltiu()
397 void Mips64Assembler::Beq(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Beq() argument
398 EmitI(0x4, rs, rt, imm16); in Beq()
402 void Mips64Assembler::Bne(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bne() argument
403 EmitI(0x5, rs, rt, imm16); in Bne()
417 void Mips64Assembler::Jalr(GpuRegister rd, GpuRegister rs) { in Jalr() argument
418 EmitR(0, rs, static_cast<GpuRegister>(0), rd, 0, 0x09); in Jalr()
422 void Mips64Assembler::Jalr(GpuRegister rs) { in Jalr() argument
423 Jalr(RA, rs); in Jalr()
426 void Mips64Assembler::Jr(GpuRegister rs) { in Jr() argument
427 Jalr(ZERO, rs); in Jr()
430 void Mips64Assembler::Auipc(GpuRegister rs, uint16_t imm16) { in Auipc() argument
431 EmitI(0x3B, rs, static_cast<GpuRegister>(0x1E), imm16); in Auipc()
442 void Mips64Assembler::Bltc(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bltc() argument
443 CHECK_NE(rs, ZERO); in Bltc()
445 CHECK_NE(rs, rt); in Bltc()
446 EmitI(0x17, rs, rt, imm16); in Bltc()
459 void Mips64Assembler::Bgec(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bgec() argument
460 CHECK_NE(rs, ZERO); in Bgec()
462 CHECK_NE(rs, rt); in Bgec()
463 EmitI(0x16, rs, rt, imm16); in Bgec()
476 void Mips64Assembler::Bltuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bltuc() argument
477 CHECK_NE(rs, ZERO); in Bltuc()
479 CHECK_NE(rs, rt); in Bltuc()
480 EmitI(0x7, rs, rt, imm16); in Bltuc()
483 void Mips64Assembler::Bgeuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bgeuc() argument
484 CHECK_NE(rs, ZERO); in Bgeuc()
486 CHECK_NE(rs, rt); in Bgeuc()
487 EmitI(0x6, rs, rt, imm16); in Bgeuc()
490 void Mips64Assembler::Beqc(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Beqc() argument
491 CHECK_NE(rs, ZERO); in Beqc()
493 CHECK_NE(rs, rt); in Beqc()
494 EmitI(0x8, (rs < rt) ? rs : rt, (rs < rt) ? rt : rs, imm16); in Beqc()
497 void Mips64Assembler::Bnec(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bnec() argument
498 CHECK_NE(rs, ZERO); in Bnec()
500 CHECK_NE(rs, rt); in Bnec()
501 EmitI(0x18, (rs < rt) ? rs : rt, (rs < rt) ? rt : rs, imm16); in Bnec()
504 void Mips64Assembler::Beqzc(GpuRegister rs, uint32_t imm21) { in Beqzc() argument
505 CHECK_NE(rs, ZERO); in Beqzc()
506 EmitI21(0x36, rs, imm21); in Beqzc()
509 void Mips64Assembler::Bnezc(GpuRegister rs, uint32_t imm21) { in Bnezc() argument
510 CHECK_NE(rs, ZERO); in Bnezc()
511 EmitI21(0x3E, rs, imm21); in Bnezc()
594 void Mips64Assembler::Lwc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) { in Lwc1() argument
595 EmitI(0x31, rs, static_cast<GpuRegister>(ft), imm16); in Lwc1()
598 void Mips64Assembler::Ldc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) { in Ldc1() argument
599 EmitI(0x35, rs, static_cast<GpuRegister>(ft), imm16); in Ldc1()
602 void Mips64Assembler::Swc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) { in Swc1() argument
603 EmitI(0x39, rs, static_cast<GpuRegister>(ft), imm16); in Swc1()
606 void Mips64Assembler::Sdc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) { in Sdc1() argument
607 EmitI(0x3d, rs, static_cast<GpuRegister>(ft), imm16); in Sdc1()
620 void Mips64Assembler::Move(GpuRegister rd, GpuRegister rs) { in Move() argument
621 Or(rd, rs, ZERO); in Move()
628 void Mips64Assembler::Not(GpuRegister rd, GpuRegister rs) { in Not() argument
629 Nor(rd, rs, ZERO); in Not()
744 void Mips64Assembler::Addiu32(GpuRegister rt, GpuRegister rs, int32_t value, GpuRegister rtmp) { in Addiu32() argument
746 Addiu(rt, rs, value); in Addiu32()
749 Addu(rt, rs, rtmp); in Addiu32()
753 void Mips64Assembler::Daddiu64(GpuRegister rt, GpuRegister rs, int64_t value, GpuRegister rtmp) { in Daddiu64() argument
755 Daddiu(rt, rs, value); in Daddiu64()
758 Daddu(rt, rs, rtmp); in Daddiu64()
875 void Mips64Assembler::Bltc(GpuRegister rs, GpuRegister rt, Label* label) { in Bltc() argument
876 Bgec(rs, rt, 2); in Bltc()
890 void Mips64Assembler::Bgec(GpuRegister rs, GpuRegister rt, Label* label) { in Bgec() argument
891 Bltc(rs, rt, 2); in Bgec()
905 void Mips64Assembler::Bltuc(GpuRegister rs, GpuRegister rt, Label* label) { in Bltuc() argument
906 Bgeuc(rs, rt, 2); in Bltuc()
910 void Mips64Assembler::Bgeuc(GpuRegister rs, GpuRegister rt, Label* label) { in Bgeuc() argument
911 Bltuc(rs, rt, 2); in Bgeuc()
915 void Mips64Assembler::Beqc(GpuRegister rs, GpuRegister rt, Label* label) { in Beqc() argument
916 Bnec(rs, rt, 2); in Beqc()
920 void Mips64Assembler::Bnec(GpuRegister rs, GpuRegister rt, Label* label) { in Bnec() argument
921 Beqc(rs, rt, 2); in Bnec()
925 void Mips64Assembler::Beqzc(GpuRegister rs, Label* label) { in Beqzc() argument
926 Bnezc(rs, 2); in Beqzc()
930 void Mips64Assembler::Bnezc(GpuRegister rs, Label* label) { in Bnezc() argument
931 Beqzc(rs, 2); in Bnezc()