Lines Matching refs:scratch
1192 Mips64ManagedRegister scratch = mscratch.AsMips64(); in StoreImmediateToFrame() local
1193 CHECK(scratch.IsGpuRegister()) << scratch; in StoreImmediateToFrame()
1194 LoadConst32(scratch.AsGpuRegister(), imm); in StoreImmediateToFrame()
1195 StoreToOffset(kStoreWord, scratch.AsGpuRegister(), SP, dest.Int32Value()); in StoreImmediateToFrame()
1200 Mips64ManagedRegister scratch = mscratch.AsMips64(); in StoreImmediateToThread64() local
1201 CHECK(scratch.IsGpuRegister()) << scratch; in StoreImmediateToThread64()
1204 LoadConst32(scratch.AsGpuRegister(), imm); in StoreImmediateToThread64()
1205 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), S1, dest.Int32Value()); in StoreImmediateToThread64()
1211 Mips64ManagedRegister scratch = mscratch.AsMips64(); in StoreStackOffsetToThread64() local
1212 CHECK(scratch.IsGpuRegister()) << scratch; in StoreStackOffsetToThread64()
1213 Daddiu64(scratch.AsGpuRegister(), SP, fr_offs.Int32Value()); in StoreStackOffsetToThread64()
1214 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value()); in StoreStackOffsetToThread64()
1224 Mips64ManagedRegister scratch = mscratch.AsMips64(); in StoreSpanning() local
1226 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), SP, in_off.Int32Value()); in StoreSpanning()
1227 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, dest.Int32Value() + 8); in StoreSpanning()
1304 Mips64ManagedRegister scratch = mscratch.AsMips64(); in CopyRef() local
1305 CHECK(scratch.IsGpuRegister()) << scratch; in CopyRef()
1306 LoadFromOffset(kLoadWord, scratch.AsGpuRegister(), SP, src.Int32Value()); in CopyRef()
1307 StoreToOffset(kStoreWord, scratch.AsGpuRegister(), SP, dest.Int32Value()); in CopyRef()
1313 Mips64ManagedRegister scratch = mscratch.AsMips64(); in CopyRawPtrFromThread64() local
1314 CHECK(scratch.IsGpuRegister()) << scratch; in CopyRawPtrFromThread64()
1315 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value()); in CopyRawPtrFromThread64()
1316 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, fr_offs.Int32Value()); in CopyRawPtrFromThread64()
1322 Mips64ManagedRegister scratch = mscratch.AsMips64(); in CopyRawPtrToThread64() local
1323 CHECK(scratch.IsGpuRegister()) << scratch; in CopyRawPtrToThread64()
1324 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), in CopyRawPtrToThread64()
1326 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), in CopyRawPtrToThread64()
1332 Mips64ManagedRegister scratch = mscratch.AsMips64(); in Copy() local
1333 CHECK(scratch.IsGpuRegister()) << scratch; in Copy()
1336 LoadFromOffset(kLoadWord, scratch.AsGpuRegister(), SP, src.Int32Value()); in Copy()
1337 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, dest.Int32Value()); in Copy()
1339 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), SP, src.Int32Value()); in Copy()
1340 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, dest.Int32Value()); in Copy()
1348 GpuRegister scratch = mscratch.AsMips64().AsGpuRegister(); in Copy() local
1351 LoadFromOffset(kLoadWord, scratch, src_base.AsMips64().AsGpuRegister(), in Copy()
1353 StoreToOffset(kStoreDoubleword, scratch, SP, dest.Int32Value()); in Copy()
1355 LoadFromOffset(kLoadDoubleword, scratch, src_base.AsMips64().AsGpuRegister(), in Copy()
1357 StoreToOffset(kStoreDoubleword, scratch, SP, dest.Int32Value()); in Copy()
1365 GpuRegister scratch = mscratch.AsMips64().AsGpuRegister(); in Copy() local
1368 LoadFromOffset(kLoadWord, scratch, SP, src.Int32Value()); in Copy()
1369 StoreToOffset(kStoreDoubleword, scratch, dest_base.AsMips64().AsGpuRegister(), in Copy()
1372 LoadFromOffset(kLoadDoubleword, scratch, SP, src.Int32Value()); in Copy()
1373 StoreToOffset(kStoreDoubleword, scratch, dest_base.AsMips64().AsGpuRegister(), in Copy()
1388 GpuRegister scratch = mscratch.AsMips64().AsGpuRegister(); in Copy() local
1391 LoadFromOffset(kLoadWord, scratch, src.AsMips64().AsGpuRegister(), src_offset.Int32Value()); in Copy()
1392 …StoreToOffset(kStoreDoubleword, scratch, dest.AsMips64().AsGpuRegister(), dest_offset.Int32Value()… in Copy()
1394 LoadFromOffset(kLoadDoubleword, scratch, src.AsMips64().AsGpuRegister(), in Copy()
1396 StoreToOffset(kStoreDoubleword, scratch, dest.AsMips64().AsGpuRegister(), in Copy()
1447 Mips64ManagedRegister scratch = mscratch.AsMips64(); in CreateHandleScopeEntry() local
1448 CHECK(scratch.IsGpuRegister()) << scratch; in CreateHandleScopeEntry()
1451 LoadFromOffset(kLoadUnsignedWord, scratch.AsGpuRegister(), SP, in CreateHandleScopeEntry()
1456 Beqzc(scratch.AsGpuRegister(), &null_arg); in CreateHandleScopeEntry()
1457 Daddiu64(scratch.AsGpuRegister(), SP, handle_scope_offset.Int32Value()); in CreateHandleScopeEntry()
1460 Daddiu64(scratch.AsGpuRegister(), SP, handle_scope_offset.Int32Value()); in CreateHandleScopeEntry()
1462 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, out_off.Int32Value()); in CreateHandleScopeEntry()
1492 Mips64ManagedRegister scratch = mscratch.AsMips64(); in Call() local
1494 CHECK(scratch.IsGpuRegister()) << scratch; in Call()
1495 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), in Call()
1497 Jalr(scratch.AsGpuRegister()); in Call()
1502 Mips64ManagedRegister scratch = mscratch.AsMips64(); in Call() local
1503 CHECK(scratch.IsGpuRegister()) << scratch; in Call()
1505 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), in Call()
1507 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), in Call()
1508 scratch.AsGpuRegister(), offset.Int32Value()); in Call()
1509 Jalr(scratch.AsGpuRegister()); in Call()
1527 Mips64ManagedRegister scratch = mscratch.AsMips64(); in ExceptionPoll() local
1528 Mips64ExceptionSlowPath* slow = new Mips64ExceptionSlowPath(scratch, stack_adjust); in ExceptionPoll()
1530 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), in ExceptionPoll()
1532 Bnezc(scratch.AsGpuRegister(), slow->Entry()); in ExceptionPoll()