Lines Matching refs:FpuRegister

160   void AddS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
161   void SubS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
162   void MulS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
163   void DivS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
164   void AddD(FpuRegister fd, FpuRegister fs, FpuRegister ft);
165   void SubD(FpuRegister fd, FpuRegister fs, FpuRegister ft);
166   void MulD(FpuRegister fd, FpuRegister fs, FpuRegister ft);
167   void DivD(FpuRegister fd, FpuRegister fs, FpuRegister ft);
168   void MovS(FpuRegister fd, FpuRegister fs);
169   void MovD(FpuRegister fd, FpuRegister fs);
170   void NegS(FpuRegister fd, FpuRegister fs);
171   void NegD(FpuRegister fd, FpuRegister fs);
173   void Cvtsw(FpuRegister fd, FpuRegister fs);
174   void Cvtdw(FpuRegister fd, FpuRegister fs);
175   void Cvtsd(FpuRegister fd, FpuRegister fs);
176   void Cvtds(FpuRegister fd, FpuRegister fs);
178   void Mfc1(GpuRegister rt, FpuRegister fs);
179   void Mtc1(GpuRegister rt, FpuRegister fs);
180   void Dmfc1(GpuRegister rt, FpuRegister fs);  // MIPS64
181   void Dmtc1(GpuRegister rt, FpuRegister fs);  // MIPS64
182   void Lwc1(FpuRegister ft, GpuRegister rs, uint16_t imm16);
183   void Ldc1(FpuRegister ft, GpuRegister rs, uint16_t imm16);
184   void Swc1(FpuRegister ft, GpuRegister rs, uint16_t imm16);
185   void Sdc1(FpuRegister ft, GpuRegister rs, uint16_t imm16);
219   void LoadFpuFromOffset(LoadOperandType type, FpuRegister reg, GpuRegister base, int32_t offset);
221   void StoreFpuToOffset(StoreOperandType type, FpuRegister reg, GpuRegister base, int32_t offset);
348   void EmitFR(int opcode, int fmt, FpuRegister ft, FpuRegister fs, FpuRegister fd, int funct);
349   void EmitFI(int opcode, int fmt, FpuRegister rt, uint16_t imm);