assembler_mips64.h - OpenGrok cross reference for /art/compiler/utils/mips64/assembler

Lines Matching refs:rs
55   void Add(GpuRegister rd, GpuRegister rs, GpuRegister rt);
56   void Addi(GpuRegister rt, GpuRegister rs, uint16_t imm16);
57   void Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
58   void Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
59   void Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
60   void Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16);  // MIPS64
61   void Sub(GpuRegister rd, GpuRegister rs, GpuRegister rt);
62   void Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
63   void Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
65   void MultR2(GpuRegister rs, GpuRegister rt);  // R2
66   void MultuR2(GpuRegister rs, GpuRegister rt);  // R2
67   void DivR2(GpuRegister rs, GpuRegister rt);  // R2
68   void DivuR2(GpuRegister rs, GpuRegister rt);  // R2
69   void MulR2(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // R2
70   void DivR2(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // R2
71   void ModR2(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // R2
72   void DivuR2(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // R2
73   void ModuR2(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // R2
74   void MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // R6
75   void DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // R6
76   void ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // R6
77   void DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // R6
78   void ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // R6
79   void Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64 R6
80   void Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64 R6
81   void Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64 R6
82   void Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64 R6
83   void Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64 R6
85   void And(GpuRegister rd, GpuRegister rs, GpuRegister rt);
86   void Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16);
87   void Or(GpuRegister rd, GpuRegister rs, GpuRegister rt);
88   void Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16);
89   void Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt);
90   void Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16);
91   void Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt);
95   void Dext(GpuRegister rs, GpuRegister rt, int pos, int size_less_one);  // MIPS64
100   void Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
101   void Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
102   void Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs);
109   void Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
110   void Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
111   void Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
113   void Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16);
114   void Lh(GpuRegister rt, GpuRegister rs, uint16_t imm16);
115   void Lw(GpuRegister rt, GpuRegister rs, uint16_t imm16);
116   void Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16);  // MIPS64
117   void Lbu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
118   void Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
119   void Lwu(GpuRegister rt, GpuRegister rs, uint16_t imm16);  // MIPS64
121   void Dahi(GpuRegister rs, uint16_t imm16);  // MIPS64 R6
122   void Dati(GpuRegister rs, uint16_t imm16);  // MIPS64 R6
127   void Sb(GpuRegister rt, GpuRegister rs, uint16_t imm16);
128   void Sh(GpuRegister rt, GpuRegister rs, uint16_t imm16);
129   void Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16);
130   void Sd(GpuRegister rt, GpuRegister rs, uint16_t imm16);  // MIPS64
132   void Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt);
133   void Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
134   void Slti(GpuRegister rt, GpuRegister rs, uint16_t imm16);
135   void Sltiu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
137   void Beq(GpuRegister rs, GpuRegister rt, uint16_t imm16);
138   void Bne(GpuRegister rs, GpuRegister rt, uint16_t imm16);
141   void Jalr(GpuRegister rd, GpuRegister rs);
142   void Jalr(GpuRegister rs);
143   void Jr(GpuRegister rs);
144   void Auipc(GpuRegister rs, uint16_t imm16);  // R6
147   void Bltc(GpuRegister rs, GpuRegister rt, uint16_t imm16);  // R6
150   void Bgec(GpuRegister rs, GpuRegister rt, uint16_t imm16);  // R6
153   void Bltuc(GpuRegister rs, GpuRegister rt, uint16_t imm16);  // R6
154   void Bgeuc(GpuRegister rs, GpuRegister rt, uint16_t imm16);  // R6
155   void Beqc(GpuRegister rs, GpuRegister rt, uint16_t imm16);  // R6
156   void Bnec(GpuRegister rs, GpuRegister rt, uint16_t imm16);  // R6
157   void Beqzc(GpuRegister rs, uint32_t imm21);  // R6
158   void Bnezc(GpuRegister rs, uint32_t imm21);  // R6
182   void Lwc1(FpuRegister ft, GpuRegister rs, uint16_t imm16);
183   void Ldc1(FpuRegister ft, GpuRegister rs, uint16_t imm16);
184   void Swc1(FpuRegister ft, GpuRegister rs, uint16_t imm16);
185   void Sdc1(FpuRegister ft, GpuRegister rs, uint16_t imm16);
189   void Move(GpuRegister rd, GpuRegister rs);
191   void Not(GpuRegister rd, GpuRegister rs);
197   void Addiu32(GpuRegister rt, GpuRegister rs, int32_t value, GpuRegister rtmp = AT);
198   void Daddiu64(GpuRegister rt, GpuRegister rs, int64_t value, GpuRegister rtmp = AT);  // MIPS64
204   void Bltc(GpuRegister rs, GpuRegister rt, Label* label);  // R6
207   void Bgec(GpuRegister rs, GpuRegister rt, Label* label);  // R6
210   void Bltuc(GpuRegister rs, GpuRegister rt, Label* label);  // R6
211   void Bgeuc(GpuRegister rs, GpuRegister rt, Label* label);  // R6
212   void Beqc(GpuRegister rs, GpuRegister rt, Label* label);  // R6
213   void Bnec(GpuRegister rs, GpuRegister rt, Label* label);  // R6
214   void Beqzc(GpuRegister rs, Label* label);  // R6
215   void Bnezc(GpuRegister rs, Label* label);  // R6
344   void EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, int shamt, int funct);
345   void EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm);
346   void EmitI21(int opcode, GpuRegister rs, uint32_t imm21);