Lines Matching refs:devid
55 #define IS_IGDGM(devid) ((devid) == PCI_CHIP_IGD_GM) argument
56 #define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G) argument
57 #define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid)) argument
184 #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ argument
185 (devid) == PCI_CHIP_I915_GM || \
186 (devid) == PCI_CHIP_I945_GM || \
187 (devid) == PCI_CHIP_I945_GME || \
188 (devid) == PCI_CHIP_I965_GM || \
189 (devid) == PCI_CHIP_I965_GME || \
190 (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
191 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
192 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2)
194 #define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \ argument
195 (devid) == PCI_CHIP_Q45_G || \
196 (devid) == PCI_CHIP_G45_G || \
197 (devid) == PCI_CHIP_G41_G)
198 #define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM) argument
199 #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid)) argument
201 #define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G) argument
202 #define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G) argument
204 #define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \ argument
205 (devid) == PCI_CHIP_E7221_G || \
206 (devid) == PCI_CHIP_I915_GM)
208 #define IS_945GM(devid) ((devid) == PCI_CHIP_I945_GM || \ argument
209 (devid) == PCI_CHIP_I945_GME)
211 #define IS_945(devid) ((devid) == PCI_CHIP_I945_G || \ argument
212 (devid) == PCI_CHIP_I945_GM || \
213 (devid) == PCI_CHIP_I945_GME || \
214 IS_G33(devid))
216 #define IS_G33(devid) ((devid) == PCI_CHIP_G33_G || \ argument
217 (devid) == PCI_CHIP_Q33_G || \
218 (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
220 #define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \ argument
221 (devid) == PCI_CHIP_845_G || \
222 (devid) == PCI_CHIP_I855_GM || \
223 (devid) == PCI_CHIP_I865_G)
225 #define IS_GEN3(devid) (IS_945(devid) || IS_915(devid)) argument
227 #define IS_GEN4(devid) ((devid) == PCI_CHIP_I965_G || \ argument
228 (devid) == PCI_CHIP_I965_Q || \
229 (devid) == PCI_CHIP_I965_G_1 || \
230 (devid) == PCI_CHIP_I965_GM || \
231 (devid) == PCI_CHIP_I965_GME || \
232 (devid) == PCI_CHIP_I946_GZ || \
233 IS_G4X(devid))
235 #define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid)) argument
237 #define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \ argument
238 (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
239 (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
240 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
241 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
242 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
243 (devid) == PCI_CHIP_SANDYBRIDGE_S)
245 #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \ argument
246 IS_HASWELL(devid) || \
247 IS_VALLEYVIEW(devid))
249 #define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \ argument
250 (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
251 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
252 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
253 (devid) == PCI_CHIP_IVYBRIDGE_S || \
254 (devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
256 #define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \ argument
257 (devid) == PCI_CHIP_VALLEYVIEW_1 || \
258 (devid) == PCI_CHIP_VALLEYVIEW_2 || \
259 (devid) == PCI_CHIP_VALLEYVIEW_3)
261 #define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \ argument
262 (devid) == PCI_CHIP_HASWELL_M_GT1 || \
263 (devid) == PCI_CHIP_HASWELL_S_GT1 || \
264 (devid) == PCI_CHIP_HASWELL_B_GT1 || \
265 (devid) == PCI_CHIP_HASWELL_E_GT1 || \
266 (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
267 (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
268 (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
269 (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
270 (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
271 (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
272 (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
273 (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
274 (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
275 (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
276 (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
277 (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
278 (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
279 (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
280 (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
281 #define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \ argument
282 (devid) == PCI_CHIP_HASWELL_M_GT2 || \
283 (devid) == PCI_CHIP_HASWELL_S_GT2 || \
284 (devid) == PCI_CHIP_HASWELL_B_GT2 || \
285 (devid) == PCI_CHIP_HASWELL_E_GT2 || \
286 (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
287 (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
288 (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
289 (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
290 (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
291 (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
292 (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
293 (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
294 (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
295 (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
296 (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
297 (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
298 (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
299 (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
300 (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
301 #define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \ argument
302 (devid) == PCI_CHIP_HASWELL_M_GT3 || \
303 (devid) == PCI_CHIP_HASWELL_S_GT3 || \
304 (devid) == PCI_CHIP_HASWELL_B_GT3 || \
305 (devid) == PCI_CHIP_HASWELL_E_GT3 || \
306 (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
307 (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
308 (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
309 (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
310 (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
311 (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
312 (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
313 (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
314 (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
315 (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
316 (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
317 (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
318 (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
319 (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
320 (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
322 #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ argument
323 IS_HSW_GT2(devid) || \
324 IS_HSW_GT3(devid))
326 #define IS_BROADWELL(devid) (((devid & 0xff00) != 0x1600) ? 0 : \ argument
327 (((devid & 0x00f0) >> 4) > 3) ? 0 : \
328 ((devid & 0x000f) == BDW_SPARE) ? 1 : \
329 ((devid & 0x000f) == BDW_ULT) ? 1 : \
330 ((devid & 0x000f) == BDW_IRIS) ? 1 : \
331 ((devid & 0x000f) == BDW_SERVER) ? 1 : \
332 ((devid & 0x000f) == BDW_WORKSTATION) ? 1 : \
333 ((devid & 0x000f) == BDW_ULX) ? 1 : 0)
335 #define IS_CHERRYVIEW(devid) ((devid) == PCI_CHIP_CHERRYVIEW_0 || \ argument
336 (devid) == PCI_CHIP_CHERRYVIEW_1 || \
337 (devid) == PCI_CHIP_CHERRYVIEW_2 || \
338 (devid) == PCI_CHIP_CHERRYVIEW_3)
340 #define IS_GEN8(devid) (IS_BROADWELL(devid) || \ argument
341 IS_CHERRYVIEW(devid))
343 #define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \ argument
344 (devid) == PCI_CHIP_SKYLAKE_ULX_GT1 || \
345 (devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \
346 (devid) == PCI_CHIP_SKYLAKE_HALO_GT1 || \
347 (devid) == PCI_CHIP_SKYLAKE_SRV_GT1)
349 #define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT2 || \ argument
350 (devid) == PCI_CHIP_SKYLAKE_ULT_GT2F || \
351 (devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \
352 (devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \
353 (devid) == PCI_CHIP_SKYLAKE_HALO_GT2 || \
354 (devid) == PCI_CHIP_SKYLAKE_SRV_GT2 || \
355 (devid) == PCI_CHIP_SKYLAKE_WKS_GT2)
357 #define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3 || \ argument
358 (devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \
359 (devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
361 #define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ argument
362 IS_SKL_GT2(devid) || \
363 IS_SKL_GT3(devid))
365 #define IS_GEN9(devid) IS_SKYLAKE(devid) argument