Lines Matching refs:LDR

52 ``LDR`` and ``LD1``
58     Big endian vector load using ``LDR``.
61 …In little endian mode, we can do this by just performing a 64-bit load - ``LDR q0, [foo]``. Howeve…
75 …1. The content of a vector register is the same *as if* it had been loaded with an ``LDR`` instruc…
78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si…
95 Use of ``LDR`` would break this lane ordering property. This doesn't preclude the use of ``LDR``, b…
97    1. Insert a ``REV`` instruction to reverse the lane order after every ``LDR``.
105 …e register; a short vector is loaded from memory using the corresponding ``LDR`` instruction. On a…
109 The use of ``LDR`` and ``STR`` as the ABI defines has at least one advantage over ``LD1`` and ``ST1…
128 So to preserve ABI compatibility, we need to use the ``LDR`` lane layout across function calls.
133 …LDR qX`` requires its address to be 128-bit aligned, whereas ``LD1`` only requires it to be as ali…
143 |                               | ``LDR`` layout                | ``LD1`` layout      |
145 | Lane ordering                 |   ``LDR + REV``               |    ``LD1``          |
147 | AAPCS                         |   ``LDR``                     |    ``LD1 + REV``    |
149 | Alignment for strict mode     |   ``LDR`` / ``LD1 + REV``     |    ``LD1``          |
159 …LDR`` and ``STR`` instructions so that they are never allowed to be selected to generate vector lo…
163 … over call boundaries as 1-element vectors (which is the same as if they were loaded with ``LDR``).
188 …g the in-register representation to the same as if it had been loaded by ``LDR``) and then insert …