Lines Matching refs:LR
216 const LiveRange &LR, unsigned Reg, unsigned LaneMask);
218 const LiveRange &LR, unsigned Reg, unsigned LaneMask);
417 const LiveRange &LR, unsigned Reg, in report() argument
420 errs() << "- liverange: " << LR << '\n'; in report()
427 const LiveRange &LR, unsigned Reg, in report() argument
430 errs() << "- liverange: " << LR << '\n'; in report()
1008 if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units)) { in checkLiveness() local
1009 LiveQueryResult LRQ = LR->Query(UseIdx); in checkLiveness()
1013 << ' ' << *LR << '\n'; in checkLiveness()
1017 errs() << PrintRegUnit(*Units, TRI) << ' ' << *LR << '\n'; in checkLiveness()
1374 if (const LiveRange *LR = LiveInts->getCachedRegUnit(i)) in verifyLiveIntervals() local
1375 verifyLiveRange(*LR, i); in verifyLiveIntervals()
1378 void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR, in verifyLiveRangeValue() argument
1384 const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def); in verifyLiveRangeValue()
1387 report("Valno not live at def and not marked unused", MF, LR, Reg, in verifyLiveRangeValue()
1394 report("Live segment at def has different valno", MF, LR, Reg, LaneMask); in verifyLiveRangeValue()
1402 report("Invalid definition index", MF, LR, Reg, LaneMask); in verifyLiveRangeValue()
1404 << " in " << LR << '\n'; in verifyLiveRangeValue()
1410 report("PHIDef value is not defined at MBB start", MBB, LR, Reg, in verifyLiveRangeValue()
1421 report("No instruction at def index", MBB, LR, Reg, LaneMask); in verifyLiveRangeValue()
1450 errs() << "Valno #" << VNI->id << " in " << LR << '\n'; in verifyLiveRangeValue()
1457 report("Early clobber def must be at an early-clobber slot", MBB, LR, in verifyLiveRangeValue()
1463 MBB, LR, Reg, LaneMask); in verifyLiveRangeValue()
1469 void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR, in verifyLiveRangeSegment() argument
1476 if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) { in verifyLiveRangeSegment()
1477 report("Foreign valno in live segment", MF, LR, Reg, LaneMask); in verifyLiveRangeSegment()
1482 report("Live segment valno is marked unused", MF, LR, Reg, LaneMask); in verifyLiveRangeSegment()
1488 report("Bad start of live segment, no basic block", MF, LR, Reg, LaneMask); in verifyLiveRangeSegment()
1494 report("Live segment must begin at MBB entry or valno def", MBB, LR, Reg, in verifyLiveRangeSegment()
1502 report("Bad end of live segment, no basic block", MF, LR, Reg, LaneMask); in verifyLiveRangeSegment()
1520 report("Live segment doesn't end at a valid instruction", EndMBB, LR, Reg, in verifyLiveRangeSegment()
1528 report("Live segment ends at B slot of an instruction", EndMBB, LR, Reg, in verifyLiveRangeSegment()
1537 report("Live segment ending at dead slot spans instructions", EndMBB, LR, in verifyLiveRangeSegment()
1546 if (I+1 == LR.end() || (I+1)->start != S.end) { in verifyLiveRangeSegment()
1548 "redefined by an EC def in the same instruction", EndMBB, LR, Reg, in verifyLiveRangeSegment()
1580 errs() << S << " in " << LR << '\n'; in verifyLiveRangeSegment()
1597 assert(LiveInts->isLiveInToMBB(LR, MFI)); in verifyLiveRangeSegment()
1615 const VNInfo *PVNI = LR.getVNInfoBefore(PEnd); in verifyLiveRangeSegment()
1619 report("Register not marked live out of predecessor", *PI, LR, Reg, in verifyLiveRangeSegment()
1629 report("Different value live out of predecessor", *PI, LR, Reg, in verifyLiveRangeSegment()
1643 void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg, in verifyLiveRange() argument
1645 for (const VNInfo *VNI : LR.valnos) in verifyLiveRange()
1646 verifyLiveRangeValue(LR, VNI, Reg, LaneMask); in verifyLiveRange()
1648 for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I) in verifyLiveRange()
1649 verifyLiveRangeSegment(LR, I, Reg, LaneMask); in verifyLiveRange()