Lines Matching refs:LR
233 void RAFast::addKillFlag(const LiveReg &LR) { in addKillFlag() argument
234 if (!LR.LastUse) return; in addKillFlag()
235 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum); in addKillFlag()
236 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) { in addKillFlag()
237 if (MO.getReg() == LR.PhysReg) in addKillFlag()
240 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true); in addKillFlag()
277 LiveReg &LR = *LRI; in spillVirtReg() local
278 assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping"); in spillVirtReg()
280 if (LR.Dirty) { in spillVirtReg()
283 bool SpillKill = LR.LastUse != MI; in spillVirtReg()
284 LR.Dirty = false; in spillVirtReg()
286 << " in " << PrintReg(LR.PhysReg, TRI)); in spillVirtReg()
290 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI); in spillVirtReg()
322 LR.LastUse = nullptr; // Don't kill register again in spillVirtReg()
498 void RAFast::assignVirtToPhysReg(LiveReg &LR, unsigned PhysReg) { in assignVirtToPhysReg() argument
499 DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to " in assignVirtToPhysReg()
501 PhysRegState[PhysReg] = LR.VirtReg; in assignVirtToPhysReg()
502 assert(!LR.PhysReg && "Already assigned a physreg"); in assignVirtToPhysReg()
503 LR.PhysReg = PhysReg; in assignVirtToPhysReg()