190     unsigned Cascade;  member
192     RegInfo() : Stage(RS_New), Cascade(0) {}  in RegInfo()
715   unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;  in canEvictInterference()  local
716   if (!Cascade)  in canEvictInterference()
717     Cascade = NextCascade;  in canEvictInterference()
745       unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;  in canEvictInterference()
746       if (Cascade <= IntfCascade) {  in canEvictInterference()
787   unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;  in evictInterference()  local
788   if (!Cascade)  in evictInterference()
789     Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;  in evictInterference()
792                << " interference: Cascade " << Cascade << '\n');  in evictInterference()
810     assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||  in evictInterference()
813     ExtraRegInfo[Intf->reg].Cascade = Cascade;  in evictInterference()
2466                << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n');  in selectOrSplitImpl()