424   bool Op0IsKill = hasTrivialKill(I->getOperand(0));  in selectBinaryOp()  local
445                                       Op0IsKill, Imm, VT.getSimpleVT());  in selectBinaryOp()
457                                      ISDOpcode, Op0, Op0IsKill, CF);  in selectBinaryOp()
472                                    ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill);  in selectBinaryOp()
1282   bool Op0IsKill = hasTrivialKill(I->getOperand(0));  in selectBitCast()  local
1299     ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);  in selectBitCast()
1654                                 bool Op0IsKill, uint64_t Imm, MVT ImmType) {  in fastEmit_ri_()  argument
1672   unsigned ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);  in fastEmit_ri_()
1685   return fastEmit_rr(VT, VT, Opcode, Op0, Op0IsKill, MaterialReg,  in fastEmit_ri_()
1721                                   bool Op0IsKill) {  in fastEmitInst_r()  argument
1729         .addReg(Op0, getKillRegState(Op0IsKill));  in fastEmitInst_r()
1732         .addReg(Op0, getKillRegState(Op0IsKill));  in fastEmitInst_r()
1742                                    bool Op0IsKill, unsigned Op1,  in fastEmitInst_rr()  argument
1752         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_rr()
1756         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_rr()
1766                                     bool Op0IsKill, unsigned Op1,  in fastEmitInst_rrr()  argument
1778         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_rrr()
1783         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_rrr()
1794                                    bool Op0IsKill, uint64_t Imm) {  in fastEmitInst_ri()  argument
1802         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_ri()
1806         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_ri()
1816                                     bool Op0IsKill, uint64_t Imm1,  in fastEmitInst_rii()  argument
1825         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_rii()
1830         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_rii()
1841                                    bool Op0IsKill, const ConstantFP *FPImm) {  in fastEmitInst_rf()  argument
1849         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_rf()
1853         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_rf()
1863                                     bool Op0IsKill, unsigned Op1,  in fastEmitInst_rri()  argument
1873         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_rri()
1878         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_rri()
1889                                      unsigned Op0, bool Op0IsKill, unsigned Op1,  in fastEmitInst_rrii()  argument
1900         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_rrii()
1906         .addReg(Op0, getKillRegState(Op0IsKill))  in fastEmitInst_rrii()
1952                                               bool Op0IsKill, uint32_t Idx) {  in fastEmitInst_extractsubreg()  argument
1959           ResultReg).addReg(Op0, getKillRegState(Op0IsKill), Idx);  in fastEmitInst_extractsubreg()
1965 unsigned FastISel::fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {  in fastEmitZExtFromI1()  argument
1966   return fastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);  in fastEmitZExtFromI1()