Lines Matching refs:DestVT

128   SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
134 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
136 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
138 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
1777 EVT DestVT, in EmitStackConvert() argument
1791 unsigned DestSize = DestVT.getSizeInBits(); in EmitStackConvert()
1792 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext()); in EmitStackConvert()
1810 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo, in EmitStackConvert()
1814 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, in EmitStackConvert()
2412 EVT DestVT, in ExpandLegalINT_TO_FP() argument
2461 if (DestVT == MVT::f64) { in ExpandLegalINT_TO_FP()
2464 } else if (DestVT.bitsLT(MVT::f64)) { in ExpandLegalINT_TO_FP()
2465 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, in ExpandLegalINT_TO_FP()
2467 } else if (DestVT.bitsGT(MVT::f64)) { in ExpandLegalINT_TO_FP()
2468 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); in ExpandLegalINT_TO_FP()
2480 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { in ExpandLegalINT_TO_FP()
2502 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) { in ExpandLegalINT_TO_FP()
2558 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2587 if (DestVT == MVT::f32) in ExpandLegalINT_TO_FP()
2592 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, in ExpandLegalINT_TO_FP()
2601 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); in ExpandLegalINT_TO_FP()
2610 EVT DestVT, in PromoteLegalINT_TO_FP() argument
2641 return DAG.getNode(OpToUse, dl, DestVT, in PromoteLegalINT_TO_FP()
2652 EVT DestVT, in PromoteLegalFP_TO_INT() argument
2656 EVT NewOutTy = DestVT; in PromoteLegalFP_TO_INT()
2687 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); in PromoteLegalFP_TO_INT()