145   std::vector<SUnit*> LiveRegGens;  member in __anon884f54d00111::ScheduleDAGRRList
332   LiveRegGens.resize(TRI->getNumRegs() + 1, nullptr);  in Schedule()
539       if (!LiveRegGens[I->getReg()]) {  in ReleasePredecessors()
541         LiveRegGens[I->getReg()] = SU;  in ReleasePredecessors()
563         LiveRegGens[CallResource] = SU;  in ReleasePredecessors()
747       LiveRegGens[I->getReg()] = nullptr;  in ScheduleNodeBottomUp()
762         LiveRegGens[CallResource] = nullptr;  in ScheduleNodeBottomUp()
812     if (I->isAssignedRegDep() && SU == LiveRegGens[I->getReg()]){  in UnscheduleNodeBottomUp()
818       LiveRegGens[I->getReg()] = nullptr;  in UnscheduleNodeBottomUp()
832       LiveRegGens[CallResource] = CallSeqEndForStart[SU];  in UnscheduleNodeBottomUp()
838   if (LiveRegGens[CallResource] == SU)  in UnscheduleNodeBottomUp()
846         LiveRegGens[CallResource] = nullptr;  in UnscheduleNodeBottomUp()
859       if (LiveRegGens[I->getReg()] == nullptr ||  in UnscheduleNodeBottomUp()
860           I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight())  in UnscheduleNodeBottomUp()
861         LiveRegGens[I->getReg()] = I->getSUnit();  in UnscheduleNodeBottomUp()
1315         SDNode *Gen = LiveRegGens[CallResource]->getNode();  in DelayForLiveRegsBottomUp()
1404       if (LiveRegGens[Reg]->getHeight() < LiveCycle) {  in PickNodeToScheduleBottomUp()
1405         BtSU = LiveRegGens[Reg];  in PickNodeToScheduleBottomUp()