Lines Matching refs:ISD
97 bool ISD::isBuildVectorAllOnes(const SDNode *N) { in isBuildVectorAllOnes()
99 while (N->getOpcode() == ISD::BITCAST) in isBuildVectorAllOnes()
102 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isBuildVectorAllOnes()
107 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) in isBuildVectorAllOnes()
137 N->getOperand(i).getOpcode() != ISD::UNDEF) in isBuildVectorAllOnes()
145 bool ISD::isBuildVectorAllZeros(const SDNode *N) { in isBuildVectorAllZeros()
147 while (N->getOpcode() == ISD::BITCAST) in isBuildVectorAllZeros()
150 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isBuildVectorAllZeros()
154 if (N->getOperand(i).getOpcode() == ISD::UNDEF) in isBuildVectorAllZeros()
185 bool ISD::isBuildVectorOfConstantSDNodes(const SDNode *N) { in isBuildVectorOfConstantSDNodes()
186 if (N->getOpcode() != ISD::BUILD_VECTOR) in isBuildVectorOfConstantSDNodes()
191 if (Op.getOpcode() == ISD::UNDEF) in isBuildVectorOfConstantSDNodes()
201 bool ISD::isBuildVectorOfConstantFPSDNodes(const SDNode *N) { in isBuildVectorOfConstantFPSDNodes()
202 if (N->getOpcode() != ISD::BUILD_VECTOR) in isBuildVectorOfConstantFPSDNodes()
207 if (Op.getOpcode() == ISD::UNDEF) in isBuildVectorOfConstantFPSDNodes()
218 bool ISD::isScalarToVector(const SDNode *N) { in isScalarToVector()
219 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) in isScalarToVector()
222 if (N->getOpcode() != ISD::BUILD_VECTOR) in isScalarToVector()
224 if (N->getOperand(0).getOpcode() == ISD::UNDEF) in isScalarToVector()
231 if (V.getOpcode() != ISD::UNDEF) in isScalarToVector()
239 bool ISD::allOperandsUndef(const SDNode *N) { in allOperandsUndef()
247 if (N->getOperand(i).getOpcode() != ISD::UNDEF) in allOperandsUndef()
253 ISD::NodeType ISD::getExtForLoadExtType(bool IsFP, ISD::LoadExtType ExtType) { in getExtForLoadExtType()
255 case ISD::EXTLOAD: in getExtForLoadExtType()
256 return IsFP ? ISD::FP_EXTEND : ISD::ANY_EXTEND; in getExtForLoadExtType()
257 case ISD::SEXTLOAD: in getExtForLoadExtType()
258 return ISD::SIGN_EXTEND; in getExtForLoadExtType()
259 case ISD::ZEXTLOAD: in getExtForLoadExtType()
260 return ISD::ZERO_EXTEND; in getExtForLoadExtType()
270 ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { in getSetCCSwappedOperands()
275 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits in getSetCCSwappedOperands()
282 ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { in getSetCCInverse()
289 if (Operation > ISD::SETTRUE2) in getSetCCInverse()
292 return ISD::CondCode(Operation); in getSetCCInverse()
299 static int isSignedOp(ISD::CondCode Opcode) { in isSignedOp()
302 case ISD::SETEQ: in isSignedOp()
303 case ISD::SETNE: return 0; in isSignedOp()
304 case ISD::SETLT: in isSignedOp()
305 case ISD::SETLE: in isSignedOp()
306 case ISD::SETGT: in isSignedOp()
307 case ISD::SETGE: return 1; in isSignedOp()
308 case ISD::SETULT: in isSignedOp()
309 case ISD::SETULE: in isSignedOp()
310 case ISD::SETUGT: in isSignedOp()
311 case ISD::SETUGE: return 2; in isSignedOp()
319 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCOrOperation()
323 return ISD::SETCC_INVALID; in getSetCCOrOperation()
329 if (Op > ISD::SETTRUE2) in getSetCCOrOperation()
333 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT in getSetCCOrOperation()
334 Op = ISD::SETNE; in getSetCCOrOperation()
336 return ISD::CondCode(Op); in getSetCCOrOperation()
343 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCAndOperation()
347 return ISD::SETCC_INVALID; in getSetCCAndOperation()
350 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); in getSetCCAndOperation()
356 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT in getSetCCAndOperation()
357 case ISD::SETOEQ: // SETEQ & SETU[LG]E in getSetCCAndOperation()
358 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE in getSetCCAndOperation()
359 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE in getSetCCAndOperation()
360 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE in getSetCCAndOperation()
428 case ISD::TargetExternalSymbol: in AddNodeIDCustom()
429 case ISD::ExternalSymbol: in AddNodeIDCustom()
432 case ISD::TargetConstant: in AddNodeIDCustom()
433 case ISD::Constant: { in AddNodeIDCustom()
439 case ISD::TargetConstantFP: in AddNodeIDCustom()
440 case ISD::ConstantFP: { in AddNodeIDCustom()
444 case ISD::TargetGlobalAddress: in AddNodeIDCustom()
445 case ISD::GlobalAddress: in AddNodeIDCustom()
446 case ISD::TargetGlobalTLSAddress: in AddNodeIDCustom()
447 case ISD::GlobalTLSAddress: { in AddNodeIDCustom()
455 case ISD::BasicBlock: in AddNodeIDCustom()
458 case ISD::Register: in AddNodeIDCustom()
461 case ISD::RegisterMask: in AddNodeIDCustom()
464 case ISD::SRCVALUE: in AddNodeIDCustom()
467 case ISD::FrameIndex: in AddNodeIDCustom()
468 case ISD::TargetFrameIndex: in AddNodeIDCustom()
471 case ISD::JumpTable: in AddNodeIDCustom()
472 case ISD::TargetJumpTable: in AddNodeIDCustom()
476 case ISD::ConstantPool: in AddNodeIDCustom()
477 case ISD::TargetConstantPool: { in AddNodeIDCustom()
488 case ISD::TargetIndex: { in AddNodeIDCustom()
495 case ISD::LOAD: { in AddNodeIDCustom()
502 case ISD::STORE: { in AddNodeIDCustom()
509 case ISD::SDIV: in AddNodeIDCustom()
510 case ISD::UDIV: in AddNodeIDCustom()
511 case ISD::SRA: in AddNodeIDCustom()
512 case ISD::SRL: in AddNodeIDCustom()
513 case ISD::MUL: in AddNodeIDCustom()
514 case ISD::ADD: in AddNodeIDCustom()
515 case ISD::SUB: in AddNodeIDCustom()
516 case ISD::SHL: { in AddNodeIDCustom()
522 case ISD::ATOMIC_CMP_SWAP: in AddNodeIDCustom()
523 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: in AddNodeIDCustom()
524 case ISD::ATOMIC_SWAP: in AddNodeIDCustom()
525 case ISD::ATOMIC_LOAD_ADD: in AddNodeIDCustom()
526 case ISD::ATOMIC_LOAD_SUB: in AddNodeIDCustom()
527 case ISD::ATOMIC_LOAD_AND: in AddNodeIDCustom()
528 case ISD::ATOMIC_LOAD_OR: in AddNodeIDCustom()
529 case ISD::ATOMIC_LOAD_XOR: in AddNodeIDCustom()
530 case ISD::ATOMIC_LOAD_NAND: in AddNodeIDCustom()
531 case ISD::ATOMIC_LOAD_MIN: in AddNodeIDCustom()
532 case ISD::ATOMIC_LOAD_MAX: in AddNodeIDCustom()
533 case ISD::ATOMIC_LOAD_UMIN: in AddNodeIDCustom()
534 case ISD::ATOMIC_LOAD_UMAX: in AddNodeIDCustom()
535 case ISD::ATOMIC_LOAD: in AddNodeIDCustom()
536 case ISD::ATOMIC_STORE: { in AddNodeIDCustom()
543 case ISD::PREFETCH: { in AddNodeIDCustom()
548 case ISD::VECTOR_SHUFFLE: { in AddNodeIDCustom()
555 case ISD::TargetBlockAddress: in AddNodeIDCustom()
556 case ISD::BlockAddress: { in AddNodeIDCustom()
588 encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, bool isVolatile, in encodeMemSDNodeFlags()
612 case ISD::HANDLENODE: in doNotCSE()
613 case ISD::EH_LABEL: in doNotCSE()
721 N->NodeType = ISD::DELETED_NODE; in DeallocateNode()
736 case ISD::BUILD_PAIR: { in VerifySDNode()
750 case ISD::BUILD_VECTOR: { in VerifySDNode()
788 case ISD::HANDLENODE: return false; // noop. in RemoveNodeFromCSEMaps()
789 case ISD::CONDCODE: in RemoveNodeFromCSEMaps()
795 case ISD::ExternalSymbol: in RemoveNodeFromCSEMaps()
798 case ISD::TargetExternalSymbol: { in RemoveNodeFromCSEMaps()
805 case ISD::VALUETYPE: { in RemoveNodeFromCSEMaps()
817 assert(N->getOpcode() != ISD::DELETED_NODE && "DELETED_NODE in CSEMap!"); in RemoveNodeFromCSEMaps()
818 assert(N->getOpcode() != ISD::EntryToken && "EntryToken in CSEMap!"); in RemoveNodeFromCSEMaps()
932 EntryNode(ISD::EntryToken, 0, DebugLoc(), getVTList(MVT::Other)), in SelectionDAG()
999 getNode(ISD::ANY_EXTEND, DL, VT, Op) : in getAnyExtOrTrunc()
1000 getNode(ISD::TRUNCATE, DL, VT, Op); in getAnyExtOrTrunc()
1005 getNode(ISD::SIGN_EXTEND, DL, VT, Op) : in getSExtOrTrunc()
1006 getNode(ISD::TRUNCATE, DL, VT, Op); in getSExtOrTrunc()
1011 getNode(ISD::ZERO_EXTEND, DL, VT, Op) : in getZExtOrTrunc()
1012 getNode(ISD::TRUNCATE, DL, VT, Op); in getZExtOrTrunc()
1018 return getNode(ISD::TRUNCATE, SL, VT, Op); in getBoolExtOrTrunc()
1032 return getNode(ISD::AND, DL, Op.getValueType(), Op, in getZeroExtendInReg()
1043 return getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, Op); in getAnyExtendVectorInReg()
1053 return getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, Op); in getSignExtendVectorInReg()
1063 return getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, VT, Op); in getZeroExtendVectorInReg()
1072 return getNode(ISD::XOR, DL, VT, Val, NegOne); in getNOT()
1088 return getNode(ISD::XOR, DL, VT, Val, TrueValue); in getLogicalNOT()
1164 SDValue Result = getNode(ISD::BITCAST, SDLoc(), VT, in getConstant()
1165 getNode(ISD::BUILD_VECTOR, SDLoc(), ViaVecVT, in getConstant()
1172 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; in getConstant()
1193 Result = getNode(ISD::BUILD_VECTOR, SDLoc(), VT, Ops); in getConstant()
1215 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; in getConstantFP()
1236 Result = getNode(ISD::BUILD_VECTOR, SDLoc(), VT, Ops); in getConstantFP()
1272 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; in getGlobalAddress()
1274 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; in getGlobalAddress()
1295 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; in getFrameIndex()
1313 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; in getJumpTable()
1337 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; in getConstantPool()
1364 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; in getConstantPool()
1385 AddNodeIDNode(ID, ISD::TargetIndex, getVTList(VT), None); in getTargetIndex()
1402 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), None); in getBasicBlock()
1447 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { in getCondCode()
1474 if (N1.getOpcode() == ISD::UNDEF && N2.getOpcode() == ISD::UNDEF) in getVectorShuffle()
1494 if (N1.getOpcode() == ISD::UNDEF) in getVectorShuffle()
1528 bool N2Undef = N2.getOpcode() == ISD::UNDEF; in getVectorShuffle()
1548 N2Undef = N2.getOpcode() == ISD::UNDEF; in getVectorShuffle()
1550 if (N1.getOpcode() == ISD::UNDEF && N2Undef) in getVectorShuffle()
1568 while (V.getOpcode() == ISD::BITCAST) in getVectorShuffle()
1576 if (Splat && Splat.getOpcode() == ISD::UNDEF) in getVectorShuffle()
1600 SDValue NewBV = getNode(ISD::BUILD_VECTOR, dl, BuildVT, Ops); in getVectorShuffle()
1605 NewBV = getNode(ISD::BITCAST, dl, VT, NewBV); in getVectorShuffle()
1613 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops); in getVectorShuffle()
1649 ISD::CvtCode Code) { in getConvertRndSat()
1653 (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF)) in getConvertRndSat()
1658 AddNodeIDNode(ID, ISD::CONVERT_RNDSAT, getVTList(VT), Ops); in getConvertRndSat()
1673 AddNodeIDNode(ID, ISD::Register, getVTList(VT), None); in getRegister()
1687 AddNodeIDNode(ID, ISD::RegisterMask, getVTList(MVT::Untyped), None); in getRegisterMask()
1702 AddNodeIDNode(ID, ISD::EH_LABEL, getVTList(MVT::Other), Ops); in getEHLabel()
1720 unsigned Opc = isTarget ? ISD::TargetBlockAddress : ISD::BlockAddress; in getBlockAddress()
1743 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), None); in getSrcValue()
1759 AddNodeIDNode(ID, ISD::MDNODE_SDNODE, getVTList(MVT::Other), None); in getMDNode()
1777 AddNodeIDNode(ID, ISD::ADDRSPACECAST, getVTList(VT), Ops); in getAddrSpaceCast()
1800 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; in getShiftAmountOperand()
1834 SDValue N2, ISD::CondCode Cond, SDLoc dl) { in FoldSetCC()
1838 case ISD::SETFALSE: in FoldSetCC()
1839 case ISD::SETFALSE2: return getConstant(0, VT); in FoldSetCC()
1840 case ISD::SETTRUE: in FoldSetCC()
1841 case ISD::SETTRUE2: { in FoldSetCC()
1848 case ISD::SETOEQ: in FoldSetCC()
1849 case ISD::SETOGT: in FoldSetCC()
1850 case ISD::SETOGE: in FoldSetCC()
1851 case ISD::SETOLT: in FoldSetCC()
1852 case ISD::SETOLE: in FoldSetCC()
1853 case ISD::SETONE: in FoldSetCC()
1854 case ISD::SETO: in FoldSetCC()
1855 case ISD::SETUO: in FoldSetCC()
1856 case ISD::SETUEQ: in FoldSetCC()
1857 case ISD::SETUNE: in FoldSetCC()
1869 case ISD::SETEQ: return getConstant(C1 == C2, VT); in FoldSetCC()
1870 case ISD::SETNE: return getConstant(C1 != C2, VT); in FoldSetCC()
1871 case ISD::SETULT: return getConstant(C1.ult(C2), VT); in FoldSetCC()
1872 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); in FoldSetCC()
1873 case ISD::SETULE: return getConstant(C1.ule(C2), VT); in FoldSetCC()
1874 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); in FoldSetCC()
1875 case ISD::SETLT: return getConstant(C1.slt(C2), VT); in FoldSetCC()
1876 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); in FoldSetCC()
1877 case ISD::SETLE: return getConstant(C1.sle(C2), VT); in FoldSetCC()
1878 case ISD::SETGE: return getConstant(C1.sge(C2), VT); in FoldSetCC()
1887 case ISD::SETEQ: if (R==APFloat::cmpUnordered) in FoldSetCC()
1890 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); in FoldSetCC()
1891 case ISD::SETNE: if (R==APFloat::cmpUnordered) in FoldSetCC()
1894 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || in FoldSetCC()
1896 case ISD::SETLT: if (R==APFloat::cmpUnordered) in FoldSetCC()
1899 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); in FoldSetCC()
1900 case ISD::SETGT: if (R==APFloat::cmpUnordered) in FoldSetCC()
1903 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); in FoldSetCC()
1904 case ISD::SETLE: if (R==APFloat::cmpUnordered) in FoldSetCC()
1907 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || in FoldSetCC()
1909 case ISD::SETGE: if (R==APFloat::cmpUnordered) in FoldSetCC()
1912 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || in FoldSetCC()
1914 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); in FoldSetCC()
1915 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); in FoldSetCC()
1916 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || in FoldSetCC()
1918 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); in FoldSetCC()
1919 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || in FoldSetCC()
1921 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || in FoldSetCC()
1923 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); in FoldSetCC()
1924 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); in FoldSetCC()
1928 ISD::CondCode SwappedCond = ISD::getSetCCSwappedOperands(Cond); in FoldSetCC()
1975 case ISD::Constant: in computeKnownBits()
1980 case ISD::AND: in computeKnownBits()
1990 case ISD::OR: in computeKnownBits()
1999 case ISD::XOR: { in computeKnownBits()
2010 case ISD::MUL: { in computeKnownBits()
2031 case ISD::UDIV: { in computeKnownBits()
2049 case ISD::SELECT: in computeKnownBits()
2057 case ISD::SELECT_CC: in computeKnownBits()
2065 case ISD::SADDO: in computeKnownBits()
2066 case ISD::UADDO: in computeKnownBits()
2067 case ISD::SSUBO: in computeKnownBits()
2068 case ISD::USUBO: in computeKnownBits()
2069 case ISD::SMULO: in computeKnownBits()
2070 case ISD::UMULO: in computeKnownBits()
2082 case ISD::SETCC: in computeKnownBits()
2089 case ISD::SHL: in computeKnownBits()
2105 case ISD::SRL: in computeKnownBits()
2122 case ISD::SRA: in computeKnownBits()
2149 case ISD::SIGN_EXTEND_INREG: { in computeKnownBits()
2184 case ISD::CTTZ: in computeKnownBits()
2185 case ISD::CTTZ_ZERO_UNDEF: in computeKnownBits()
2186 case ISD::CTLZ: in computeKnownBits()
2187 case ISD::CTLZ_ZERO_UNDEF: in computeKnownBits()
2188 case ISD::CTPOP: { in computeKnownBits()
2194 case ISD::LOAD: { in computeKnownBits()
2197 if (ISD::isZEXTLoad(Op.getNode()) && Op.getResNo() == 0) { in computeKnownBits()
2206 case ISD::ZERO_EXTEND: { in computeKnownBits()
2218 case ISD::SIGN_EXTEND: { in computeKnownBits()
2241 case ISD::ANY_EXTEND: { in computeKnownBits()
2251 case ISD::TRUNCATE: { in computeKnownBits()
2261 case ISD::AssertZext: { in computeKnownBits()
2269 case ISD::FGETSIGN: in computeKnownBits()
2274 case ISD::SUB: { in computeKnownBits()
2297 case ISD::ADD: in computeKnownBits()
2298 case ISD::ADDE: { in computeKnownBits()
2309 if (Op.getOpcode() == ISD::ADD) { in computeKnownBits()
2322 case ISD::SREM: in computeKnownBits()
2346 case ISD::UREM: { in computeKnownBits()
2371 case ISD::EXTRACT_ELEMENT: { in computeKnownBits()
2386 case ISD::FrameIndex: in computeKnownBits()
2387 case ISD::TargetFrameIndex: in computeKnownBits()
2396 if (Op.getOpcode() < ISD::BUILTIN_OP_END) in computeKnownBits()
2399 case ISD::INTRINSIC_WO_CHAIN: in computeKnownBits()
2400 case ISD::INTRINSIC_W_CHAIN: in computeKnownBits()
2401 case ISD::INTRINSIC_VOID: in computeKnownBits()
2427 case ISD::AssertSext: in ComputeNumSignBits()
2430 case ISD::AssertZext: in ComputeNumSignBits()
2434 case ISD::Constant: { in ComputeNumSignBits()
2439 case ISD::SIGN_EXTEND: in ComputeNumSignBits()
2444 case ISD::SIGN_EXTEND_INREG: in ComputeNumSignBits()
2453 case ISD::SRA: in ComputeNumSignBits()
2461 case ISD::SHL: in ComputeNumSignBits()
2470 case ISD::AND: in ComputeNumSignBits()
2471 case ISD::OR: in ComputeNumSignBits()
2472 case ISD::XOR: // NOT is handled here. in ComputeNumSignBits()
2484 case ISD::SELECT: in ComputeNumSignBits()
2490 case ISD::SADDO: in ComputeNumSignBits()
2491 case ISD::UADDO: in ComputeNumSignBits()
2492 case ISD::SSUBO: in ComputeNumSignBits()
2493 case ISD::USUBO: in ComputeNumSignBits()
2494 case ISD::SMULO: in ComputeNumSignBits()
2495 case ISD::UMULO: in ComputeNumSignBits()
2506 case ISD::SETCC: in ComputeNumSignBits()
2512 case ISD::ROTL: in ComputeNumSignBits()
2513 case ISD::ROTR: in ComputeNumSignBits()
2518 if (Op.getOpcode() == ISD::ROTR) in ComputeNumSignBits()
2527 case ISD::ADD: in ComputeNumSignBits()
2554 case ISD::SUB: in ComputeNumSignBits()
2581 case ISD::TRUNCATE: in ComputeNumSignBits()
2585 case ISD::EXTRACT_ELEMENT: { in ComputeNumSignBits()
2609 case ISD::SEXTLOAD: // '17' bits known in ComputeNumSignBits()
2612 case ISD::ZEXTLOAD: // '16' bits known in ComputeNumSignBits()
2620 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || in ComputeNumSignBits()
2621 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || in ComputeNumSignBits()
2622 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || in ComputeNumSignBits()
2623 Op.getOpcode() == ISD::INTRINSIC_VOID) { in ComputeNumSignBits()
2658 if ((Op.getOpcode() != ISD::ADD && Op.getOpcode() != ISD::OR) || in isBaseWithConstantOffset()
2662 if (Op.getOpcode() == ISD::OR && in isBaseWithConstantOffset()
2693 case ISD::OR: in isKnownNeverZero()
2743 case ISD::SIGN_EXTEND: in getNode()
2746 case ISD::ANY_EXTEND: in getNode()
2747 case ISD::ZERO_EXTEND: in getNode()
2748 case ISD::TRUNCATE: in getNode()
2751 case ISD::UINT_TO_FP: in getNode()
2752 case ISD::SINT_TO_FP: { in getNode()
2756 Opcode==ISD::SINT_TO_FP, in getNode()
2760 case ISD::BITCAST: in getNode()
2768 case ISD::BSWAP: in getNode()
2771 case ISD::CTPOP: in getNode()
2774 case ISD::CTLZ: in getNode()
2775 case ISD::CTLZ_ZERO_UNDEF: in getNode()
2778 case ISD::CTTZ: in getNode()
2779 case ISD::CTTZ_ZERO_UNDEF: in getNode()
2789 case ISD::FNEG: in getNode()
2792 case ISD::FABS: in getNode()
2795 case ISD::FCEIL: { in getNode()
2801 case ISD::FTRUNC: { in getNode()
2807 case ISD::FFLOOR: { in getNode()
2813 case ISD::FP_EXTEND: { in getNode()
2821 case ISD::FP_TO_SINT: in getNode()
2822 case ISD::FP_TO_UINT: { in getNode()
2828 Opcode==ISD::FP_TO_SINT, in getNode()
2835 case ISD::BITCAST: in getNode()
2854 case ISD::TRUNCATE: in getNode()
2857 return getNode(ISD::BUILD_VECTOR, DL, VT, BV->ops()); in getNode()
2858 case ISD::FNEG: in getNode()
2859 case ISD::FABS: in getNode()
2860 case ISD::FCEIL: in getNode()
2861 case ISD::FTRUNC: in getNode()
2862 case ISD::FFLOOR: in getNode()
2863 case ISD::FP_EXTEND: in getNode()
2864 case ISD::UINT_TO_FP: in getNode()
2865 case ISD::SINT_TO_FP: { in getNode()
2871 if (OpN.getOpcode() != ISD::UNDEF && in getNode()
2872 OpN.getOpcode() != ISD::Constant && in getNode()
2873 OpN.getOpcode() != ISD::ConstantFP) in getNode()
2878 return getNode(ISD::BUILD_VECTOR, DL, VT, Ops); in getNode()
2887 case ISD::TokenFactor: in getNode()
2888 case ISD::MERGE_VALUES: in getNode()
2889 case ISD::CONCAT_VECTORS: in getNode()
2891 case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node"); in getNode()
2892 case ISD::FP_EXTEND: in getNode()
2900 if (Operand.getOpcode() == ISD::UNDEF) in getNode()
2903 case ISD::SIGN_EXTEND: in getNode()
2913 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) in getNode()
2915 else if (OpOpcode == ISD::UNDEF) in getNode()
2919 case ISD::ZERO_EXTEND: in getNode()
2929 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) in getNode()
2930 return getNode(ISD::ZERO_EXTEND, DL, VT, in getNode()
2932 else if (OpOpcode == ISD::UNDEF) in getNode()
2936 case ISD::ANY_EXTEND: in getNode()
2947 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || in getNode()
2948 OpOpcode == ISD::ANY_EXTEND) in getNode()
2951 else if (OpOpcode == ISD::UNDEF) in getNode()
2955 if (OpOpcode == ISD::TRUNCATE) { in getNode()
2961 case ISD::TRUNCATE: in getNode()
2971 if (OpOpcode == ISD::TRUNCATE) in getNode()
2972 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); in getNode()
2973 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || in getNode()
2974 OpOpcode == ISD::ANY_EXTEND) { in getNode()
2980 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); in getNode()
2983 if (OpOpcode == ISD::UNDEF) in getNode()
2986 case ISD::BITCAST: in getNode()
2991 if (OpOpcode == ISD::BITCAST) // bitconv(bitconv(x)) -> bitconv(x) in getNode()
2992 return getNode(ISD::BITCAST, DL, VT, Operand.getOperand(0)); in getNode()
2993 if (OpOpcode == ISD::UNDEF) in getNode()
2996 case ISD::SCALAR_TO_VECTOR: in getNode()
3003 if (OpOpcode == ISD::UNDEF) in getNode()
3006 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && in getNode()
3012 case ISD::FNEG: in getNode()
3014 if (getTarget().Options.UnsafeFPMath && OpOpcode == ISD::FSUB) in getNode()
3015 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1), in getNode()
3017 if (OpOpcode == ISD::FNEG) // --X -> X in getNode()
3020 case ISD::FABS: in getNode()
3021 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) in getNode()
3022 return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0)); in getNode()
3053 if (Opcode >= ISD::BUILTIN_OP_END) in FoldConstantArithmetic()
3102 case ISD::ADD: in FoldConstantArithmetic()
3105 case ISD::SUB: in FoldConstantArithmetic()
3108 case ISD::MUL: in FoldConstantArithmetic()
3111 case ISD::UDIV: in FoldConstantArithmetic()
3116 case ISD::UREM: in FoldConstantArithmetic()
3121 case ISD::SDIV: in FoldConstantArithmetic()
3126 case ISD::SREM: in FoldConstantArithmetic()
3131 case ISD::AND: in FoldConstantArithmetic()
3134 case ISD::OR: in FoldConstantArithmetic()
3137 case ISD::XOR: in FoldConstantArithmetic()
3140 case ISD::SHL: in FoldConstantArithmetic()
3143 case ISD::SRL: in FoldConstantArithmetic()
3146 case ISD::SRA: in FoldConstantArithmetic()
3149 case ISD::ROTL: in FoldConstantArithmetic()
3152 case ISD::ROTR: in FoldConstantArithmetic()
3171 return getNode(ISD::BUILD_VECTOR, SDLoc(), VT, Outputs); in FoldConstantArithmetic()
3180 case ISD::TokenFactor: in getNode()
3184 if (N1.getOpcode() == ISD::EntryToken) return N2; in getNode()
3185 if (N2.getOpcode() == ISD::EntryToken) return N1; in getNode()
3188 case ISD::CONCAT_VECTORS: in getNode()
3190 if (N1.getOpcode() == ISD::UNDEF && in getNode()
3191 N2.getOpcode() == ISD::UNDEF) in getNode()
3196 if (N1.getOpcode() == ISD::BUILD_VECTOR && in getNode()
3197 N2.getOpcode() == ISD::BUILD_VECTOR) { in getNode()
3201 return getNode(ISD::BUILD_VECTOR, DL, VT, Elts); in getNode()
3204 case ISD::AND: in getNode()
3215 case ISD::OR: in getNode()
3216 case ISD::XOR: in getNode()
3217 case ISD::ADD: in getNode()
3218 case ISD::SUB: in getNode()
3227 case ISD::UDIV: in getNode()
3228 case ISD::UREM: in getNode()
3229 case ISD::MULHU: in getNode()
3230 case ISD::MULHS: in getNode()
3231 case ISD::MUL: in getNode()
3232 case ISD::SDIV: in getNode()
3233 case ISD::SREM: in getNode()
3238 case ISD::FADD: in getNode()
3239 case ISD::FSUB: in getNode()
3240 case ISD::FMUL: in getNode()
3241 case ISD::FDIV: in getNode()
3242 case ISD::FREM: in getNode()
3244 if (Opcode == ISD::FADD) { in getNode()
3253 } else if (Opcode == ISD::FSUB) { in getNode()
3258 } else if (Opcode == ISD::FMUL) { in getNode()
3282 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. in getNode()
3288 case ISD::SHL: in getNode()
3289 case ISD::SRA: in getNode()
3290 case ISD::SRL: in getNode()
3291 case ISD::ROTL: in getNode()
3292 case ISD::ROTR: in getNode()
3315 case ISD::FP_ROUND_INREG: { in getNode()
3331 case ISD::FP_ROUND: in getNode()
3338 case ISD::AssertSext: in getNode()
3339 case ISD::AssertZext: { in getNode()
3351 case ISD::SIGN_EXTEND_INREG: { in getNode()
3374 case ISD::EXTRACT_VECTOR_ELT: in getNode()
3376 if (N1.getOpcode() == ISD::UNDEF) in getNode()
3382 N1.getOpcode() == ISD::CONCAT_VECTORS && in getNode()
3386 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, in getNode()
3394 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) { in getNode()
3408 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { in getNode()
3423 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2); in getNode()
3427 case ISD::EXTRACT_ELEMENT: in getNode()
3437 if (N1.getOpcode() == ISD::BUILD_PAIR) in getNode()
3448 case ISD::EXTRACT_SUBVECTOR: { in getNode()
3498 case ISD::FADD: in getNode()
3503 case ISD::FSUB: in getNode()
3508 case ISD::FMUL: in getNode()
3513 case ISD::FDIV: in getNode()
3520 case ISD::FREM : in getNode()
3527 case ISD::FCOPYSIGN: in getNode()
3534 if (Opcode == ISD::FP_ROUND) { in getNode()
3546 if (N1.getOpcode() == ISD::UNDEF) { in getNode()
3551 case ISD::FP_ROUND_INREG: in getNode()
3552 case ISD::SIGN_EXTEND_INREG: in getNode()
3553 case ISD::SUB: in getNode()
3554 case ISD::FSUB: in getNode()
3555 case ISD::FDIV: in getNode()
3556 case ISD::FREM: in getNode()
3557 case ISD::SRA: in getNode()
3559 case ISD::UDIV: in getNode()
3560 case ISD::SDIV: in getNode()
3561 case ISD::UREM: in getNode()
3562 case ISD::SREM: in getNode()
3563 case ISD::SRL: in getNode()
3564 case ISD::SHL: in getNode()
3575 if (N2.getOpcode() == ISD::UNDEF) { in getNode()
3577 case ISD::XOR: in getNode()
3578 if (N1.getOpcode() == ISD::UNDEF) in getNode()
3583 case ISD::ADD: in getNode()
3584 case ISD::ADDC: in getNode()
3585 case ISD::ADDE: in getNode()
3586 case ISD::SUB: in getNode()
3587 case ISD::UDIV: in getNode()
3588 case ISD::SDIV: in getNode()
3589 case ISD::UREM: in getNode()
3590 case ISD::SREM: in getNode()
3592 case ISD::FADD: in getNode()
3593 case ISD::FSUB: in getNode()
3594 case ISD::FMUL: in getNode()
3595 case ISD::FDIV: in getNode()
3596 case ISD::FREM: in getNode()
3600 case ISD::MUL: in getNode()
3601 case ISD::AND: in getNode()
3602 case ISD::SRL: in getNode()
3603 case ISD::SHL: in getNode()
3609 case ISD::OR: in getNode()
3615 case ISD::SRA: in getNode()
3650 case ISD::FMA: { in getNode()
3665 case ISD::CONCAT_VECTORS: in getNode()
3668 if (N1.getOpcode() == ISD::BUILD_VECTOR && in getNode()
3669 N2.getOpcode() == ISD::BUILD_VECTOR && in getNode()
3670 N3.getOpcode() == ISD::BUILD_VECTOR) { in getNode()
3675 return getNode(ISD::BUILD_VECTOR, DL, VT, Elts); in getNode()
3678 case ISD::SETCC: { in getNode()
3684 case ISD::SELECT: in getNode()
3693 case ISD::VECTOR_SHUFFLE: in getNode()
3695 case ISD::INSERT_SUBVECTOR: { in getNode()
3719 case ISD::BITCAST: in getNode()
3782 return getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains); in getStackArgumentTokenFactor()
3789 assert(Value.getOpcode() != ISD::UNDEF); in getMemsetValue()
3805 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, IntVT, Value); in getMemsetValue()
3810 Value = DAG.getNode(ISD::MUL, dl, IntVT, Value, in getMemsetValue()
3815 Value = DAG.getNode(ISD::BITCAST, dl, VT.getScalarType(), Value); in getMemsetValue()
3820 Value = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, BVOps); in getMemsetValue()
3840 return DAG.getNode(ISD::BITCAST, dl, VT, in getMemsetStringVal()
3874 return DAG.getNode(ISD::ADD, dl, in getMemBasePlusOffset()
3883 if (Src.getOpcode() == ISD::GlobalAddress) in isMemSrcFromString()
3885 else if (Src.getOpcode() == ISD::ADD && in isMemSrcFromString()
3886 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && in isMemSrcFromString()
3887 Src.getOperand(1).getOpcode() == ISD::Constant) { in isMemSrcFromString()
3957 if (TLI.isOperationLegalOrCustom(ISD::STORE, NewVT) && in FindOptimalMemOpLowering()
3961 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::f64) && in FindOptimalMemOpLowering()
4012 if (Src.getOpcode() == ISD::UNDEF) in getMemcpyLoadsAndStores()
4101 Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain, in getMemcpyLoadsAndStores()
4116 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in getMemcpyLoadsAndStores()
4127 if (Src.getOpcode() == ISD::UNDEF) in getMemmoveLoadsAndStores()
4180 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains); in getMemmoveLoadsAndStores()
4194 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in getMemmoveLoadsAndStores()
4221 if (Src.getOpcode() == ISD::UNDEF) in getMemsetStores()
4280 Value = DAG.getNode(ISD::TRUNCATE, dl, VT, MemSetValue); in getMemsetStores()
4294 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in getMemsetStores()
4528 assert(Opcode == ISD::ATOMIC_CMP_SWAP || in getAtomicCmpSwap()
4529 Opcode == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS); in getAtomicCmpSwap()
4557 assert(Opcode == ISD::ATOMIC_CMP_SWAP || in getAtomicCmpSwap()
4558 Opcode == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS); in getAtomicCmpSwap()
4584 if (Opcode != ISD::ATOMIC_STORE) in getAtomic()
4586 if (Opcode != ISD::ATOMIC_LOAD) in getAtomic()
4603 assert((Opcode == ISD::ATOMIC_LOAD_ADD || in getAtomic()
4604 Opcode == ISD::ATOMIC_LOAD_SUB || in getAtomic()
4605 Opcode == ISD::ATOMIC_LOAD_AND || in getAtomic()
4606 Opcode == ISD::ATOMIC_LOAD_OR || in getAtomic()
4607 Opcode == ISD::ATOMIC_LOAD_XOR || in getAtomic()
4608 Opcode == ISD::ATOMIC_LOAD_NAND || in getAtomic()
4609 Opcode == ISD::ATOMIC_LOAD_MIN || in getAtomic()
4610 Opcode == ISD::ATOMIC_LOAD_MAX || in getAtomic()
4611 Opcode == ISD::ATOMIC_LOAD_UMIN || in getAtomic()
4612 Opcode == ISD::ATOMIC_LOAD_UMAX || in getAtomic()
4613 Opcode == ISD::ATOMIC_SWAP || in getAtomic()
4614 Opcode == ISD::ATOMIC_STORE) && in getAtomic()
4619 SDVTList VTs = Opcode == ISD::ATOMIC_STORE ? getVTList(MVT::Other) : in getAtomic()
4631 assert(Opcode == ISD::ATOMIC_LOAD && "Invalid Atomic Op"); in getAtomic()
4647 return getNode(ISD::MERGE_VALUES, dl, getVTList(VTs), Ops); in getMergeValues()
4679 assert((Opcode == ISD::INTRINSIC_VOID || in getMemIntrinsicNode()
4680 Opcode == ISD::INTRINSIC_W_CHAIN || in getMemIntrinsicNode()
4681 Opcode == ISD::PREFETCH || in getMemIntrinsicNode()
4682 Opcode == ISD::LIFETIME_START || in getMemIntrinsicNode()
4683 Opcode == ISD::LIFETIME_END || in getMemIntrinsicNode()
4685 (int)Opcode >= ISD::FIRST_TARGET_MEMORY_OPCODE)) && in getMemIntrinsicNode()
4723 if (Ptr.getOpcode() != ISD::ADD || in InferPointerInfo()
4741 if (OffsetOp.getOpcode() == ISD::UNDEF) in InferPointerInfo()
4748 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad()
4781 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad()
4786 ExtType = ISD::NON_EXTLOAD; in getLoad()
4787 } else if (ExtType == ISD::NON_EXTLOAD) { in getLoad()
4802 bool Indexed = AM != ISD::UNINDEXED; in getLoad()
4803 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && in getLoad()
4810 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops); in getLoad()
4837 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
4846 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
4850 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, in getExtLoad()
4857 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, in getExtLoad()
4863 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, in getExtLoad()
4867 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, in getExtLoad()
4873 SDValue Offset, ISD::MemIndexedMode AM) { in getIndexedLoad()
4875 assert(LD->getOffset().getOpcode() == ISD::UNDEF && in getIndexedLoad()
4919 AddNodeIDNode(ID, ISD::STORE, VTs, Ops); in getStore()
4921 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, MMO->isVolatile(), in getStore()
4931 ISD::UNINDEXED, false, VT, MMO); in getStore()
4988 AddNodeIDNode(ID, ISD::STORE, VTs, Ops); in getTruncStore()
4990 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, MMO->isVolatile(), in getTruncStore()
5000 ISD::UNINDEXED, true, SVT, MMO); in getTruncStore()
5008 SDValue Offset, ISD::MemIndexedMode AM) { in getIndexedStore()
5010 assert(ST->getOffset().getOpcode() == ISD::UNDEF && in getIndexedStore()
5015 AddNodeIDNode(ID, ISD::STORE, VTs, Ops); in getIndexedStore()
5036 MachineMemOperand *MMO, ISD::LoadExtType ExtTy) { in getMaskedLoad()
5041 AddNodeIDNode(ID, ISD::MLOAD, VTs, Ops); in getMaskedLoad()
5043 ID.AddInteger(encodeMemSDNodeFlags(ExtTy, ISD::UNINDEXED, in getMaskedLoad()
5070 AddNodeIDNode(ID, ISD::MSTORE, VTs, Ops); in getMaskedStore()
5072 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, MMO->isVolatile(), in getMaskedStore()
5093 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops); in getVAArg()
5125 case ISD::SELECT_CC: { in getNode()
5135 case ISD::BR_CC: { in getNode()
5182 case ISD::SRA_PARTS: in getNode()
5183 case ISD::SRL_PARTS: in getNode()
5184 case ISD::SHL_PARTS: in getNode()
5185 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && in getNode()
5188 else if (N3.getOpcode() == ISD::AND) in getNode()
6303 assert(AllNodes.front().getOpcode() == ISD::EntryToken && in AssignTopologicalOrder()
6369 : UnarySDNode(ISD::ADDRSPACECAST, Order, dl, getSDVTList(VT), X), in AddrSpaceCastSDNode()
6375 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, MMO->isVolatile(), in MemSDNode()
6390 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, MMO->isVolatile(), in MemSDNode()
6510 if (getOpcode() == ISD::TokenFactor) { in reachesChainWithoutSideEffects()
6594 Operands[j] = getNode(ISD::EXTRACT_VECTOR_ELT, dl, in UnrollVectorOp()
6608 case ISD::VSELECT: in UnrollVectorOp()
6609 Scalars.push_back(getNode(ISD::SELECT, dl, EltVT, Operands)); in UnrollVectorOp()
6611 case ISD::SHL: in UnrollVectorOp()
6612 case ISD::SRA: in UnrollVectorOp()
6613 case ISD::SRL: in UnrollVectorOp()
6614 case ISD::ROTL: in UnrollVectorOp()
6615 case ISD::ROTR: in UnrollVectorOp()
6620 case ISD::SIGN_EXTEND_INREG: in UnrollVectorOp()
6621 case ISD::FP_ROUND_INREG: { in UnrollVectorOp()
6633 return getNode(ISD::BUILD_VECTOR, dl, in UnrollVectorOp()
6651 if (Loc.getOpcode() == ISD::FrameIndex) { in isConsecutiveLoad()
6652 if (BaseLoc.getOpcode() != ISD::FrameIndex) in isConsecutiveLoad()
6759 Lo = getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N, in SplitVector()
6761 Hi = getNode(ISD::EXTRACT_SUBVECTOR, DL, HiVT, N, in SplitVector()
6777 Args.push_back(getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, in ExtractVectorElements()
6822 if (OpVal.getOpcode() == ISD::UNDEF) in isConstantSplat()
6868 if (Op.getOpcode() == ISD::UNDEF) { in getSplatValue()
6879 assert(getOperand(0).getOpcode() == ISD::UNDEF && in getSplatValue()
6902 if (Opc != ISD::UNDEF && Opc != ISD::Constant && Opc != ISD::ConstantFP) in isConstant()