Lines Matching refs:ISD
122 ISD::CondCode &CCCode, in softenSetCCOperands()
130 case ISD::SETEQ: in softenSetCCOperands()
131 case ISD::SETOEQ: in softenSetCCOperands()
135 case ISD::SETNE: in softenSetCCOperands()
136 case ISD::SETUNE: in softenSetCCOperands()
140 case ISD::SETGE: in softenSetCCOperands()
141 case ISD::SETOGE: in softenSetCCOperands()
145 case ISD::SETLT: in softenSetCCOperands()
146 case ISD::SETOLT: in softenSetCCOperands()
150 case ISD::SETLE: in softenSetCCOperands()
151 case ISD::SETOLE: in softenSetCCOperands()
155 case ISD::SETGT: in softenSetCCOperands()
156 case ISD::SETOGT: in softenSetCCOperands()
160 case ISD::SETUO: in softenSetCCOperands()
164 case ISD::SETO: in softenSetCCOperands()
172 case ISD::SETONE: in softenSetCCOperands()
177 case ISD::SETUGT: in softenSetCCOperands()
181 case ISD::SETUGE: in softenSetCCOperands()
185 case ISD::SETULT: in softenSetCCOperands()
189 case ISD::SETULE: in softenSetCCOperands()
193 case ISD::SETUEQ: in softenSetCCOperands()
209 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, in softenSetCCOperands()
214 NewLHS = DAG.getNode(ISD::SETCC, dl, in softenSetCCOperands()
217 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS); in softenSetCCOperands()
292 case ISD::XOR: in ShrinkDemandedConstant()
293 case ISD::AND: in ShrinkDemandedConstant()
294 case ISD::OR: { in ShrinkDemandedConstant()
298 if (Op.getOpcode() == ISD::XOR && in ShrinkDemandedConstant()
355 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
357 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
360 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND, in ShrinkDemandedOp()
403 if (Op.getOpcode() != ISD::UNDEF) in SimplifyDemandedBits()
412 case ISD::Constant: in SimplifyDemandedBits()
417 case ISD::AND: in SimplifyDemandedBits()
465 case ISD::OR: in SimplifyDemandedBits()
499 case ISD::XOR: in SimplifyDemandedBits()
523 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), in SimplifyDemandedBits()
541 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, in SimplifyDemandedBits()
569 case ISD::SELECT: in SimplifyDemandedBits()
587 case ISD::SELECT_CC: in SimplifyDemandedBits()
605 case ISD::SHL: in SimplifyDemandedBits()
617 if (InOp.getOpcode() == ISD::SRL && in SimplifyDemandedBits()
621 unsigned Opc = ISD::SHL; in SimplifyDemandedBits()
625 Opc = ISD::SRL; in SimplifyDemandedBits()
642 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { in SimplifyDemandedBits()
647 isTypeDesirableForOp(ISD::SHL, InnerVT)) { in SimplifyDemandedBits()
652 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, in SimplifyDemandedBits()
656 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), in SimplifyDemandedBits()
665 InnerOp.getOpcode() == ISD::SRL && in SimplifyDemandedBits()
678 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, in SimplifyDemandedBits()
680 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT, in SimplifyDemandedBits()
692 case ISD::SRL: in SimplifyDemandedBits()
706 if (InOp.getOpcode() == ISD::SHL && in SimplifyDemandedBits()
710 unsigned Opc = ISD::SRL; in SimplifyDemandedBits()
714 Opc = ISD::SHL; in SimplifyDemandedBits()
736 case ISD::SRA: in SimplifyDemandedBits()
743 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), in SimplifyDemandedBits()
775 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, in SimplifyDemandedBits()
785 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, in SimplifyDemandedBits()
794 case ISD::SIGN_EXTEND_INREG: { in SimplifyDemandedBits()
815 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, in SimplifyDemandedBits()
864 case ISD::BUILD_PAIR: { in SimplifyDemandedBits()
889 case ISD::ZERO_EXTEND: { in SimplifyDemandedBits()
898 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, in SimplifyDemandedBits()
911 case ISD::SIGN_EXTEND: { in SimplifyDemandedBits()
920 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, in SimplifyDemandedBits()
938 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, in SimplifyDemandedBits()
952 case ISD::ANY_EXTEND: { in SimplifyDemandedBits()
964 case ISD::TRUNCATE: { in SimplifyDemandedBits()
982 case ISD::SRL: in SimplifyDemandedBits()
986 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) in SimplifyDemandedBits()
1007 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, in SimplifyDemandedBits()
1010 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, in SimplifyDemandedBits()
1022 case ISD::AssertZext: { in SimplifyDemandedBits()
1036 case ISD::BITCAST: in SimplifyDemandedBits()
1044 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); in SimplifyDemandedBits()
1045 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); in SimplifyDemandedBits()
1050 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); in SimplifyDemandedBits()
1053 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); in SimplifyDemandedBits()
1056 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, in SimplifyDemandedBits()
1062 case ISD::ADD: in SimplifyDemandedBits()
1063 case ISD::MUL: in SimplifyDemandedBits()
1064 case ISD::SUB: { in SimplifyDemandedBits()
1102 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || in computeKnownBitsForTargetNode()
1103 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || in computeKnownBitsForTargetNode()
1104 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || in computeKnownBitsForTargetNode()
1105 Op.getOpcode() == ISD::INTRINSIC_VOID) && in computeKnownBitsForTargetNode()
1117 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || in ComputeNumSignBitsForTargetNode()
1118 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || in ComputeNumSignBitsForTargetNode()
1119 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || in ComputeNumSignBitsForTargetNode()
1120 Op.getOpcode() == ISD::INTRINSIC_VOID) && in ComputeNumSignBitsForTargetNode()
1133 if (Val.getOpcode() == ISD::SHL) in ValueHasExactlyOneBitSet()
1141 if (Val.getOpcode() == ISD::SRL) in ValueHasExactlyOneBitSet()
1217 ISD::CondCode Cond, bool foldBooleans, in SimplifySetCC()
1224 case ISD::SETFALSE: in SimplifySetCC()
1225 case ISD::SETFALSE2: return DAG.getConstant(0, VT); in SimplifySetCC()
1226 case ISD::SETTRUE: in SimplifySetCC()
1227 case ISD::SETTRUE2: { in SimplifySetCC()
1237 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond); in SimplifySetCC()
1249 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && in SimplifySetCC()
1250 N0.getOperand(0).getOpcode() == ISD::CTLZ && in SimplifySetCC()
1251 N0.getOperand(1).getOpcode() == ISD::Constant) { in SimplifySetCC()
1254 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1256 if ((C1 == 0) == (Cond == ISD::SETEQ)) { in SimplifySetCC()
1259 Cond = ISD::SETNE; in SimplifySetCC()
1263 Cond = ISD::SETEQ; in SimplifySetCC()
1273 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE) in SimplifySetCC()
1276 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP && in SimplifySetCC()
1284 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
1285 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp, in SimplifySetCC()
1287 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub); in SimplifySetCC()
1288 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
1297 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1302 if (N0->getOpcode() == ISD::ZERO_EXTEND) { in SimplifySetCC()
1306 } else if (N0->getOpcode() == ISD::AND) { in SimplifySetCC()
1313 } else if (N0->getOpcode() == ISD::SIGN_EXTEND) { in SimplifySetCC()
1320 if (LN0->getExtensionType() == ISD::ZEXTLOAD) { in SimplifySetCC()
1323 } else if (LN0->getExtensionType() == ISD::SEXTLOAD) { in SimplifySetCC()
1340 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { in SimplifySetCC()
1342 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt); in SimplifySetCC()
1353 !ISD::isSignedIntSetCC(Cond) && in SimplifySetCC()
1354 N0.getOpcode() == ISD::AND && C1 == 0 && in SimplifySetCC()
1367 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) in SimplifySetCC()
1393 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), in SimplifySetCC()
1400 DAG.getNode(ISD::AND, dl, newVT, NewLoad, in SimplifySetCC()
1409 if (N0.getOpcode() == ISD::ZERO_EXTEND) { in SimplifySetCC()
1417 case ISD::SETUGT: in SimplifySetCC()
1418 case ISD::SETUGE: in SimplifySetCC()
1419 case ISD::SETEQ: return DAG.getConstant(0, VT); in SimplifySetCC()
1420 case ISD::SETULT: in SimplifySetCC()
1421 case ISD::SETULE: in SimplifySetCC()
1422 case ISD::SETNE: return DAG.getConstant(1, VT); in SimplifySetCC()
1423 case ISD::SETGT: in SimplifySetCC()
1424 case ISD::SETGE: in SimplifySetCC()
1427 case ISD::SETLT: in SimplifySetCC()
1428 case ISD::SETLE: in SimplifySetCC()
1438 case ISD::SETEQ: in SimplifySetCC()
1439 case ISD::SETNE: in SimplifySetCC()
1440 case ISD::SETUGT: in SimplifySetCC()
1441 case ISD::SETUGE: in SimplifySetCC()
1442 case ISD::SETULT: in SimplifySetCC()
1443 case ISD::SETULE: { in SimplifySetCC()
1446 (isOperationLegal(ISD::SETCC, newVT) && in SimplifySetCC()
1460 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && in SimplifySetCC()
1461 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { in SimplifySetCC()
1470 return DAG.getConstant(Cond == ISD::SETNE, VT); in SimplifySetCC()
1478 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), in SimplifySetCC()
1491 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { in SimplifySetCC()
1493 if (N0.getOpcode() == ISD::SETCC && in SimplifySetCC()
1495 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); in SimplifySetCC()
1497 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); in SimplifySetCC()
1499 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); in SimplifySetCC()
1500 CC = ISD::getSetCCInverse(CC, in SimplifySetCC()
1507 if ((N0.getOpcode() == ISD::XOR || in SimplifySetCC()
1508 (N0.getOpcode() == ISD::AND && in SimplifySetCC()
1509 N0.getOperand(0).getOpcode() == ISD::XOR && in SimplifySetCC()
1521 if (N0.getOpcode() == ISD::XOR) in SimplifySetCC()
1524 assert(N0.getOpcode() == ISD::AND && in SimplifySetCC()
1525 N0.getOperand(0).getOpcode() == ISD::XOR); in SimplifySetCC()
1527 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), in SimplifySetCC()
1533 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); in SimplifySetCC()
1540 if (Op0.getOpcode() == ISD::TRUNCATE) in SimplifySetCC()
1543 if ((Op0.getOpcode() == ISD::XOR) && in SimplifySetCC()
1544 Op0.getOperand(0).getOpcode() == ISD::SETCC && in SimplifySetCC()
1545 Op0.getOperand(1).getOpcode() == ISD::SETCC) { in SimplifySetCC()
1547 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; in SimplifySetCC()
1551 if (Op0.getOpcode() == ISD::AND && in SimplifySetCC()
1556 Op0 = DAG.getNode(ISD::AND, dl, VT, in SimplifySetCC()
1557 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), in SimplifySetCC()
1560 Op0 = DAG.getNode(ISD::AND, dl, VT, in SimplifySetCC()
1561 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), in SimplifySetCC()
1566 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); in SimplifySetCC()
1568 if (Op0.getOpcode() == ISD::AssertZext && in SimplifySetCC()
1572 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); in SimplifySetCC()
1578 if (ISD::isSignedIntSetCC(Cond)) { in SimplifySetCC()
1587 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { in SimplifySetCC()
1591 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; in SimplifySetCC()
1602 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { in SimplifySetCC()
1606 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
1617 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) in SimplifySetCC()
1619 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) in SimplifySetCC()
1621 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) in SimplifySetCC()
1623 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) in SimplifySetCC()
1627 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) in SimplifySetCC()
1628 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); in SimplifySetCC()
1630 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) in SimplifySetCC()
1631 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); in SimplifySetCC()
1634 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) in SimplifySetCC()
1637 ISD::SETEQ); in SimplifySetCC()
1639 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) in SimplifySetCC()
1642 ISD::SETEQ); in SimplifySetCC()
1648 if (Cond == ISD::SETUGT && in SimplifySetCC()
1652 ISD::SETLT); in SimplifySetCC()
1655 if (Cond == ISD::SETULT && in SimplifySetCC()
1660 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); in SimplifySetCC()
1664 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1667 N0.getOpcode() == ISD::AND) in SimplifySetCC()
1672 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 in SimplifySetCC()
1675 return DAG.getNode(ISD::TRUNCATE, dl, VT, in SimplifySetCC()
1676 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, in SimplifySetCC()
1679 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { in SimplifySetCC()
1683 return DAG.getNode(ISD::TRUNCATE, dl, VT, in SimplifySetCC()
1684 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, in SimplifySetCC()
1693 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1694 N0.getOpcode() == ISD::AND && N0.hasOneUse()) { in SimplifySetCC()
1703 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0), in SimplifySetCC()
1709 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || in SimplifySetCC()
1710 Cond == ISD::SETULE || Cond == ISD::SETUGT) { in SimplifySetCC()
1711 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT); in SimplifySetCC()
1718 ISD::CondCode NewCond = Cond; in SimplifySetCC()
1722 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in SimplifySetCC()
1731 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0, in SimplifySetCC()
1749 switch (ISD::getUnorderedFlavor(Cond)) { in SimplifySetCC()
1764 if (Cond == ISD::SETO || Cond == ISD::SETUO) in SimplifySetCC()
1775 if (Cond == ISD::SETOEQ && in SimplifySetCC()
1776 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) in SimplifySetCC()
1777 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); in SimplifySetCC()
1778 if (Cond == ISD::SETUEQ && in SimplifySetCC()
1779 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) in SimplifySetCC()
1780 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); in SimplifySetCC()
1781 if (Cond == ISD::SETUNE && in SimplifySetCC()
1782 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType())) in SimplifySetCC()
1783 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); in SimplifySetCC()
1784 if (Cond == ISD::SETONE && in SimplifySetCC()
1785 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType())) in SimplifySetCC()
1786 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); in SimplifySetCC()
1788 if (Cond == ISD::SETOEQ && in SimplifySetCC()
1789 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) in SimplifySetCC()
1790 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); in SimplifySetCC()
1791 if (Cond == ISD::SETUEQ && in SimplifySetCC()
1792 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) in SimplifySetCC()
1793 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); in SimplifySetCC()
1794 if (Cond == ISD::SETUNE && in SimplifySetCC()
1795 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType())) in SimplifySetCC()
1796 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); in SimplifySetCC()
1797 if (Cond == ISD::SETONE && in SimplifySetCC()
1798 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType())) in SimplifySetCC()
1799 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); in SimplifySetCC()
1812 EqVal = ISD::isTrueWhenEqual(Cond); in SimplifySetCC()
1815 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0; in SimplifySetCC()
1823 unsigned UOF = ISD::getUnorderedFlavor(Cond); in SimplifySetCC()
1826 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) in SimplifySetCC()
1830 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; in SimplifySetCC()
1836 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1838 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || in SimplifySetCC()
1839 N0.getOpcode() == ISD::XOR) { in SimplifySetCC()
1864 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { in SimplifySetCC()
1872 if (N0.getOpcode() == ISD::XOR) in SimplifySetCC()
1886 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { in SimplifySetCC()
1914 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); in SimplifySetCC()
1916 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1, in SimplifySetCC()
1926 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || in SimplifySetCC()
1927 N1.getOpcode() == ISD::XOR) { in SimplifySetCC()
1937 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); in SimplifySetCC()
1939 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, in SimplifySetCC()
1952 if (N0.getOpcode() == ISD::AND) in SimplifySetCC()
1955 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); in SimplifySetCC()
1963 if (N1.getOpcode() == ISD::AND) in SimplifySetCC()
1966 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); in SimplifySetCC()
1981 case ISD::SETEQ: // X == Y -> ~(X^Y) in SimplifySetCC()
1982 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); in SimplifySetCC()
1987 case ISD::SETNE: // X != Y --> (X^Y) in SimplifySetCC()
1988 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); in SimplifySetCC()
1990 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y in SimplifySetCC()
1991 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y in SimplifySetCC()
1993 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); in SimplifySetCC()
1997 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X in SimplifySetCC()
1998 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X in SimplifySetCC()
2000 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); in SimplifySetCC()
2004 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y in SimplifySetCC()
2005 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y in SimplifySetCC()
2007 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); in SimplifySetCC()
2011 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X in SimplifySetCC()
2012 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X in SimplifySetCC()
2014 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); in SimplifySetCC()
2021 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); in SimplifySetCC()
2041 if (N->getOpcode() == ISD::ADD) { in isGAPlusOffset()
2139 if (Op.getOpcode() == ISD::BasicBlock) { in LowerAsmOperandForConstraint()
2154 if (Op.getOpcode() == ISD::ADD) { in LowerAsmOperandForConstraint()
2653 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, false, false, in BuildExactSDIV()
2664 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2); in BuildExactSDIV()
2689 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : in BuildSDIV()
2690 isOperationLegalOrCustom(ISD::MULHS, VT)) in BuildSDIV()
2691 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), in BuildSDIV()
2693 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) : in BuildSDIV()
2694 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) in BuildSDIV()
2695 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), in BuildSDIV()
2702 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); in BuildSDIV()
2707 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); in BuildSDIV()
2712 Q = DAG.getNode(ISD::SRA, dl, VT, Q, in BuildSDIV()
2717 SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q, in BuildSDIV()
2721 return DAG.getNode(ISD::ADD, dl, VT, Q, T); in BuildSDIV()
2751 Q = DAG.getNode(ISD::SRL, dl, VT, Q, in BuildUDIV()
2762 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : in BuildUDIV()
2763 isOperationLegalOrCustom(ISD::MULHU, VT)) in BuildUDIV()
2764 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT)); in BuildUDIV()
2765 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) : in BuildUDIV()
2766 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) in BuildUDIV()
2767 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q, in BuildUDIV()
2777 return DAG.getNode(ISD::SRL, dl, VT, Q, in BuildUDIV()
2780 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); in BuildUDIV()
2782 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, in BuildUDIV()
2785 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); in BuildUDIV()
2787 return DAG.getNode(ISD::SRL, dl, VT, NPQ, in BuildUDIV()
2813 bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT); in expandMUL()
2814 bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT); in expandMUL()
2815 bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT); in expandMUL()
2816 bool HasUMUL_LOHI = isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT); in expandMUL()
2828 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) { in expandMUL()
2829 LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(0)); in expandMUL()
2830 RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(1)); in expandMUL()
2842 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL, in expandMUL()
2849 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL); in expandMUL()
2850 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL); in expandMUL()
2858 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL, in expandMUL()
2865 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL); in expandMUL()
2866 Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL); in expandMUL()
2872 isOperationLegalOrCustom(ISD::SRL, VT) && in expandMUL()
2873 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) { in expandMUL()
2876 LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift); in expandMUL()
2877 LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH); in expandMUL()
2878 RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift); in expandMUL()
2879 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH); in expandMUL()
2887 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl, in expandMUL()
2891 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH); in expandMUL()
2892 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL); in expandMUL()
2893 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH); in expandMUL()
2894 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH); in expandMUL()
2898 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL); in expandMUL()
2899 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL); in expandMUL()
2900 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH); in expandMUL()
2901 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL); in expandMUL()
2902 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH); in expandMUL()
2903 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH); in expandMUL()
2933 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0)); in expandFP_TO_SINT()
2935 SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT, in expandFP_TO_SINT()
2936 DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), in expandFP_TO_SINT()
2938 SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias); in expandFP_TO_SINT()
2940 SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT, in expandFP_TO_SINT()
2941 DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask), in expandFP_TO_SINT()
2945 SDValue R = DAG.getNode(ISD::OR, dl, IntVT, in expandFP_TO_SINT()
2946 DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask), in expandFP_TO_SINT()
2953 DAG.getNode(ISD::SHL, dl, NVT, R, in expandFP_TO_SINT()
2955 DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit), in expandFP_TO_SINT()
2957 DAG.getNode(ISD::SRL, dl, NVT, R, in expandFP_TO_SINT()
2959 DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent), in expandFP_TO_SINT()
2961 ISD::SETGT); in expandFP_TO_SINT()
2963 SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT, in expandFP_TO_SINT()
2964 DAG.getNode(ISD::XOR, dl, NVT, R, Sign), in expandFP_TO_SINT()
2968 DAG.getConstant(0, NVT), Ret, ISD::SETLT); in expandFP_TO_SINT()