Lines Matching refs:SRL
617 if (InOp.getOpcode() == ISD::SRL && in SimplifyDemandedBits()
625 Opc = ISD::SRL; in SimplifyDemandedBits()
665 InnerOp.getOpcode() == ISD::SRL && in SimplifyDemandedBits()
692 case ISD::SRL: in SimplifyDemandedBits()
710 unsigned Opc = ISD::SRL; in SimplifyDemandedBits()
743 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), in SimplifyDemandedBits()
775 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, in SimplifyDemandedBits()
785 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, in SimplifyDemandedBits()
982 case ISD::SRL: in SimplifyDemandedBits()
986 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) in SimplifyDemandedBits()
1010 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, in SimplifyDemandedBits()
1141 if (Val.getOpcode() == ISD::SRL) in ValueHasExactlyOneBitSet()
1249 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && in SimplifySetCC()
1676 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, in SimplifySetCC()
1684 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, in SimplifySetCC()
1703 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0), in SimplifySetCC()
1731 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0, in SimplifySetCC()
2717 SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q, in BuildSDIV()
2751 Q = DAG.getNode(ISD::SRL, dl, VT, Q, in BuildUDIV()
2777 return DAG.getNode(ISD::SRL, dl, VT, Q, in BuildUDIV()
2782 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, in BuildUDIV()
2787 return DAG.getNode(ISD::SRL, dl, VT, NPQ, in BuildUDIV()
2872 isOperationLegalOrCustom(ISD::SRL, VT) && in expandMUL()
2876 LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift); in expandMUL()
2878 RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift); in expandMUL()
2935 SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT, in expandFP_TO_SINT()
2957 DAG.getNode(ISD::SRL, dl, NVT, R, in expandFP_TO_SINT()