Lines Matching refs:VT
120 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, in softenSetCCOperands() argument
124 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128) in softenSetCCOperands()
132 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : in softenSetCCOperands()
133 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128; in softenSetCCOperands()
137 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : in softenSetCCOperands()
138 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128; in softenSetCCOperands()
142 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : in softenSetCCOperands()
143 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128; in softenSetCCOperands()
147 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : in softenSetCCOperands()
148 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128; in softenSetCCOperands()
152 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : in softenSetCCOperands()
153 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128; in softenSetCCOperands()
157 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : in softenSetCCOperands()
158 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128; in softenSetCCOperands()
161 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : in softenSetCCOperands()
162 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128; in softenSetCCOperands()
165 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : in softenSetCCOperands()
166 (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128; in softenSetCCOperands()
169 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : in softenSetCCOperands()
170 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128; in softenSetCCOperands()
174 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : in softenSetCCOperands()
175 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128; in softenSetCCOperands()
178 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : in softenSetCCOperands()
179 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128; in softenSetCCOperands()
182 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : in softenSetCCOperands()
183 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128; in softenSetCCOperands()
186 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : in softenSetCCOperands()
187 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128; in softenSetCCOperands()
190 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : in softenSetCCOperands()
191 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128; in softenSetCCOperands()
194 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : in softenSetCCOperands()
195 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128; in softenSetCCOperands()
304 EVT VT = Op.getValueType(); in ShrinkDemandedConstant() local
305 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), in ShrinkDemandedConstant()
308 VT)); in ShrinkDemandedConstant()
539 EVT VT = Op.getValueType(); in SimplifyDemandedBits() local
540 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); in SimplifyDemandedBits()
541 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, in SimplifyDemandedBits()
554 EVT VT = Op.getValueType(); in SimplifyDemandedBits() local
555 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), in SimplifyDemandedBits()
556 TLO.DAG.getConstant(Expanded, VT)); in SimplifyDemandedBits()
630 EVT VT = Op.getValueType(); in SimplifyDemandedBits() local
631 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, in SimplifyDemandedBits()
677 EVT VT = Op.getValueType(); in SimplifyDemandedBits() local
678 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, in SimplifyDemandedBits()
680 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT, in SimplifyDemandedBits()
694 EVT VT = Op.getValueType(); in SimplifyDemandedBits() local
696 unsigned VTSize = VT.getSizeInBits(); in SimplifyDemandedBits()
719 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, in SimplifyDemandedBits()
747 EVT VT = Op.getValueType(); in SimplifyDemandedBits() local
760 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); in SimplifyDemandedBits()
775 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, in SimplifyDemandedBits()
785 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, in SimplifyDemandedBits()
1025 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in SimplifyDemandedBits() local
1027 VT.getSizeInBits()); in SimplifyDemandedBits()
1216 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, in SimplifySetCC() argument
1225 case ISD::SETFALSE2: return DAG.getConstant(0, VT); in SimplifySetCC()
1231 Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, VT); in SimplifySetCC()
1241 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC); in SimplifySetCC()
1266 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), in SimplifySetCC()
1289 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC); in SimplifySetCC()
1344 return DAG.getSetCC(dl, VT, Trunc, C, Cond); in SimplifySetCC()
1399 return DAG.getSetCC(dl, VT, in SimplifySetCC()
1419 case ISD::SETEQ: return DAG.getConstant(0, VT); in SimplifySetCC()
1422 case ISD::SETNE: return DAG.getConstant(1, VT); in SimplifySetCC()
1426 return DAG.getConstant(C1.isNegative(), VT); in SimplifySetCC()
1430 return DAG.getConstant(C1.isNonNegative(), VT); in SimplifySetCC()
1453 return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType()); in SimplifySetCC()
1470 return DAG.getConstant(Cond == ISD::SETNE, VT); in SimplifySetCC()
1484 return DAG.getSetCC(dl, VT, ZextOp, in SimplifySetCC()
1494 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { in SimplifySetCC()
1497 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); in SimplifySetCC()
1504 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); in SimplifySetCC()
1532 return DAG.getSetCC(dl, VT, Val, N1, in SimplifySetCC()
1536 (VT == MVT::i1 || in SimplifySetCC()
1548 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), in SimplifySetCC()
1555 if (Op0.getValueType().bitsGT(VT)) in SimplifySetCC()
1556 Op0 = DAG.getNode(ISD::AND, dl, VT, in SimplifySetCC()
1557 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), in SimplifySetCC()
1558 DAG.getConstant(1, VT)); in SimplifySetCC()
1559 else if (Op0.getValueType().bitsLT(VT)) in SimplifySetCC()
1560 Op0 = DAG.getNode(ISD::AND, dl, VT, in SimplifySetCC()
1561 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), in SimplifySetCC()
1562 DAG.getConstant(1, VT)); in SimplifySetCC()
1564 return DAG.getSetCC(dl, VT, Op0, in SimplifySetCC()
1570 return DAG.getSetCC(dl, VT, Op0, in SimplifySetCC()
1588 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true in SimplifySetCC()
1593 isCondCodeLegal(NewCC, VT.getSimpleVT())) && in SimplifySetCC()
1596 return DAG.getSetCC(dl, VT, N0, in SimplifySetCC()
1603 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true in SimplifySetCC()
1608 isCondCodeLegal(NewCC, VT.getSimpleVT())) && in SimplifySetCC()
1611 return DAG.getSetCC(dl, VT, N0, in SimplifySetCC()
1618 return DAG.getConstant(0, VT); // X < MIN --> false in SimplifySetCC()
1620 return DAG.getConstant(1, VT); // X >= MIN --> true in SimplifySetCC()
1622 return DAG.getConstant(0, VT); // X > MAX --> false in SimplifySetCC()
1624 return DAG.getConstant(1, VT); // X <= MAX --> true in SimplifySetCC()
1628 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); in SimplifySetCC()
1631 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); in SimplifySetCC()
1635 return DAG.getSetCC(dl, VT, N0, in SimplifySetCC()
1640 return DAG.getSetCC(dl, VT, N0, in SimplifySetCC()
1650 return DAG.getSetCC(dl, VT, N0, in SimplifySetCC()
1660 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); in SimplifySetCC()
1665 (VT == N0.getValueType() || in SimplifySetCC()
1666 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && in SimplifySetCC()
1675 return DAG.getNode(ISD::TRUNCATE, dl, VT, in SimplifySetCC()
1683 return DAG.getNode(ISD::TRUNCATE, dl, VT, in SimplifySetCC()
1706 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond); in SimplifySetCC()
1734 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond); in SimplifySetCC()
1742 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); in SimplifySetCC()
1752 return DAG.getConstant(0, VT); in SimplifySetCC()
1754 return DAG.getConstant(1, VT); in SimplifySetCC()
1756 return DAG.getUNDEF(VT); in SimplifySetCC()
1765 return DAG.getSetCC(dl, VT, N0, N0, Cond); in SimplifySetCC()
1777 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); in SimplifySetCC()
1780 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); in SimplifySetCC()
1783 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); in SimplifySetCC()
1786 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); in SimplifySetCC()
1790 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); in SimplifySetCC()
1793 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); in SimplifySetCC()
1796 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); in SimplifySetCC()
1799 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); in SimplifySetCC()
1821 return DAG.getConstant(EqVal, VT); in SimplifySetCC()
1825 return DAG.getConstant(EqVal, VT); in SimplifySetCC()
1827 return DAG.getConstant(EqVal, VT); in SimplifySetCC()
1833 return DAG.getSetCC(dl, VT, N0, N1, NewCond); in SimplifySetCC()
1843 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); in SimplifySetCC()
1845 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); in SimplifySetCC()
1849 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), in SimplifySetCC()
1852 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), in SimplifySetCC()
1865 return DAG.getSetCC(dl, VT, N0.getOperand(0), in SimplifySetCC()
1877 DAG.getSetCC(dl, VT, N0.getOperand(0), in SimplifySetCC()
1888 DAG.getSetCC(dl, VT, N0.getOperand(1), in SimplifySetCC()
1907 return DAG.getSetCC(dl, VT, N0.getOperand(1), in SimplifySetCC()
1911 return DAG.getSetCC(dl, VT, N0.getOperand(0), in SimplifySetCC()
1920 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); in SimplifySetCC()
1930 return DAG.getSetCC(dl, VT, N1.getOperand(1), in SimplifySetCC()
1934 return DAG.getSetCC(dl, VT, N1.getOperand(0), in SimplifySetCC()
1943 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); in SimplifySetCC()
1959 return DAG.getSetCC(dl, VT, N0, Zero, Cond); in SimplifySetCC()
1970 return DAG.getSetCC(dl, VT, N1, Zero, Cond); in SimplifySetCC()
2017 if (VT != MVT::i1) { in SimplifySetCC()
2021 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); in SimplifySetCC()
2196 MVT VT) const { in getRegForInlineAsmConstraint()
2226 if (RC->hasType(VT)) in getRegForInlineAsmConstraint()
2676 EVT VT = N->getValueType(0); in BuildSDIV() local
2681 if (!isTypeLegal(VT)) in BuildSDIV()
2689 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : in BuildSDIV()
2690 isOperationLegalOrCustom(ISD::MULHS, VT)) in BuildSDIV()
2691 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), in BuildSDIV()
2692 DAG.getConstant(magics.m, VT)); in BuildSDIV()
2693 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) : in BuildSDIV()
2694 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) in BuildSDIV()
2695 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), in BuildSDIV()
2697 DAG.getConstant(magics.m, VT)).getNode(), 1); in BuildSDIV()
2702 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); in BuildSDIV()
2707 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); in BuildSDIV()
2712 Q = DAG.getNode(ISD::SRA, dl, VT, Q, in BuildSDIV()
2717 SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q, in BuildSDIV()
2718 DAG.getConstant(VT.getScalarSizeInBits() - 1, in BuildSDIV()
2721 return DAG.getNode(ISD::ADD, dl, VT, Q, T); in BuildSDIV()
2733 EVT VT = N->getValueType(0); in BuildUDIV() local
2738 if (!isTypeLegal(VT)) in BuildUDIV()
2751 Q = DAG.getNode(ISD::SRL, dl, VT, Q, in BuildUDIV()
2762 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : in BuildUDIV()
2763 isOperationLegalOrCustom(ISD::MULHU, VT)) in BuildUDIV()
2764 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT)); in BuildUDIV()
2765 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) : in BuildUDIV()
2766 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) in BuildUDIV()
2767 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q, in BuildUDIV()
2768 DAG.getConstant(magics.m, VT)).getNode(), 1); in BuildUDIV()
2777 return DAG.getNode(ISD::SRL, dl, VT, Q, in BuildUDIV()
2780 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); in BuildUDIV()
2782 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, in BuildUDIV()
2785 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); in BuildUDIV()
2787 return DAG.getNode(ISD::SRL, dl, VT, NPQ, in BuildUDIV()
2810 EVT VT = N->getValueType(0); in expandMUL() local
2818 unsigned OuterBitSize = VT.getSizeInBits(); in expandMUL()
2872 isOperationLegalOrCustom(ISD::SRL, VT) && in expandMUL()
2874 unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits(); in expandMUL()
2875 SDValue Shift = DAG.getConstant(ShiftAmt, getShiftAmountTy(VT)); in expandMUL()
2876 LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift); in expandMUL()
2878 RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift); in expandMUL()
2912 EVT VT = Node->getOperand(0).getValueType(); in expandFP_TO_SINT() local
2917 if (VT != MVT::f32 || NVT != MVT::i64) in expandFP_TO_SINT()
2924 VT.getSizeInBits()); in expandFP_TO_SINT()
2928 SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()), in expandFP_TO_SINT()
2930 SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, IntVT); in expandFP_TO_SINT()