Lines Matching refs:VT
667 RTLIB::Libcall RTLIB::getATOMIC(unsigned Opc, MVT VT) { in getATOMIC() argument
670 switch (VT.SimpleTy) { \ in getATOMIC()
789 for (MVT VT : MVT::all_valuetypes()) { in initActions() local
793 setIndexedLoadAction(IM, VT, Expand); in initActions()
794 setIndexedStoreAction(IM, VT, Expand); in initActions()
798 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); in initActions()
801 setOperationAction(ISD::FGETSIGN, VT, Expand); in initActions()
802 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); in initActions()
803 setOperationAction(ISD::FMINNUM, VT, Expand); in initActions()
804 setOperationAction(ISD::FMAXNUM, VT, Expand); in initActions()
805 setOperationAction(ISD::FMAD, VT, Expand); in initActions()
808 setOperationAction(ISD::FROUND, VT, Expand); in initActions()
811 if (VT.isVector()) { in initActions()
812 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in initActions()
813 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
814 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
815 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
832 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) { in initActions()
833 setOperationAction(ISD::FLOG , VT, Expand); in initActions()
834 setOperationAction(ISD::FLOG2, VT, Expand); in initActions()
835 setOperationAction(ISD::FLOG10, VT, Expand); in initActions()
836 setOperationAction(ISD::FEXP , VT, Expand); in initActions()
837 setOperationAction(ISD::FEXP2, VT, Expand); in initActions()
838 setOperationAction(ISD::FFLOOR, VT, Expand); in initActions()
839 setOperationAction(ISD::FMINNUM, VT, Expand); in initActions()
840 setOperationAction(ISD::FMAXNUM, VT, Expand); in initActions()
841 setOperationAction(ISD::FNEARBYINT, VT, Expand); in initActions()
842 setOperationAction(ISD::FCEIL, VT, Expand); in initActions()
843 setOperationAction(ISD::FRINT, VT, Expand); in initActions()
844 setOperationAction(ISD::FTRUNC, VT, Expand); in initActions()
845 setOperationAction(ISD::FROUND, VT, Expand); in initActions()
883 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { in canOpTrap()
884 assert(isTypeLegal(VT)); in canOpTrap()
899 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { in getTypeConversion()
901 if (VT.isSimple()) { in getTypeConversion()
902 MVT SVT = VT.getSimpleVT(); in getTypeConversion()
921 if (!VT.isVector()) { in getTypeConversion()
922 assert(VT.isInteger() && "Float types must be simple"); in getTypeConversion()
923 unsigned BitSize = VT.getSizeInBits(); in getTypeConversion()
926 EVT NVT = VT.getRoundIntegerType(Context); in getTypeConversion()
927 assert(NVT != VT && "Unable to round integer VT"); in getTypeConversion()
937 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); in getTypeConversion()
941 unsigned NumElts = VT.getVectorNumElements(); in getTypeConversion()
942 EVT EltVT = VT.getVectorElementType(); in getTypeConversion()
954 if (!VT.isPow2VectorType()) { in getTypeConversion()
1021 if (!VT.isPow2VectorType()) { in getTypeConversion()
1022 EVT NVT = VT.getPow2VectorType(Context); in getTypeConversion()
1027 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); in getTypeConversion()
1031 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, in getVectorTypeBreakdownMVT() argument
1036 unsigned NumElts = VT.getVectorNumElements(); in getVectorTypeBreakdownMVT()
1037 MVT EltTy = VT.getVectorElementType(); in getVectorTypeBreakdownMVT()
1153 MVT VT) const { in findRepresentativeClass()
1154 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; in findRepresentativeClass()
1277 MVT VT = (MVT::SimpleValueType) i; in computeRegisterProperties() local
1278 if (isTypeLegal(VT)) in computeRegisterProperties()
1281 MVT EltVT = VT.getVectorElementType(); in computeRegisterProperties()
1282 unsigned NElts = VT.getVectorNumElements(); in computeRegisterProperties()
1284 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); in computeRegisterProperties()
1299 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); in computeRegisterProperties()
1316 ValueTypeActions.setTypeAction(VT, TypeWidenVector); in computeRegisterProperties()
1329 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT, in computeRegisterProperties()
1333 MVT NVT = VT.getPow2VectorType(); in computeRegisterProperties()
1334 if (NVT == VT) { in computeRegisterProperties()
1338 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); in computeRegisterProperties()
1340 ValueTypeActions.setTypeAction(VT, TypeSplitVector); in computeRegisterProperties()
1343 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector in computeRegisterProperties()
1347 ValueTypeActions.setTypeAction(VT, TypeWidenVector); in computeRegisterProperties()
1370 EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const { in getSetCCResultType()
1371 assert(!VT.isVector() && "No default SetCC type for vectors!"); in getSetCCResultType()
1388 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, in getVectorTypeBreakdown() argument
1392 unsigned NumElts = VT.getVectorNumElements(); in getVectorTypeBreakdown()
1399 LegalizeTypeAction TA = getTypeAction(Context, VT); in getVectorTypeBreakdown()
1401 EVT RegisterEVT = getTypeToTransformTo(Context, VT); in getVectorTypeBreakdown()
1411 EVT EltTy = VT.getVectorElementType(); in getVectorTypeBreakdown()
1466 EVT VT = ValueVTs[j]; in GetReturnInfo() local
1478 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { in GetReturnInfo()
1480 if (VT.bitsLT(MinVT)) in GetReturnInfo()
1481 VT = MinVT; in GetReturnInfo()
1484 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); in GetReturnInfo()
1485 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); in GetReturnInfo()
1499 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0)); in GetReturnInfo()