44 class AArch64FastISel final : public FastISel {  class
247   explicit AArch64FastISel(FunctionLoweringInfo &FuncInfo,  in AArch64FastISel()  function in __anoncec764240111::AArch64FastISel
303 CCAssignFn *AArch64FastISel::CCAssignFnForCall(CallingConv::ID CC) const {  in CCAssignFnForCall()
311 unsigned AArch64FastISel::fastMaterializeAlloca(const AllocaInst *AI) {  in fastMaterializeAlloca()
335 unsigned AArch64FastISel::materializeInt(const ConstantInt *CI, MVT VT) {  in materializeInt()
352 unsigned AArch64FastISel::materializeFP(const ConstantFP *CFP, MVT VT) {  in materializeFP()
410 unsigned AArch64FastISel::materializeGV(const GlobalValue *GV) {  in materializeGV()
460 unsigned AArch64FastISel::fastMaterializeConstant(const Constant *C) {  in fastMaterializeConstant()
478 unsigned AArch64FastISel::fastMaterializeFloatZero(const ConstantFP* CFP) {  in fastMaterializeFloatZero()
508 bool AArch64FastISel::computeAddress(const Value *Obj, Address &Addr, Type *Ty)  in computeAddress()
854 bool AArch64FastISel::computeCallAddress(const Value *V, Address &Addr) {  in computeCallAddress()
904 bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) {  in isTypeLegal()
925 bool AArch64FastISel::isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed) {  in isTypeSupported()
940 bool AArch64FastISel::isValueAvailable(const Value *V) const {  in isValueAvailable()
951 bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) {  in simplifyAddress()
1044 void AArch64FastISel::addLoadStoreOperands(Address &Addr,  in addLoadStoreOperands()
1084 unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,  in emitAddSub()
1231 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,  in emitAddSub_rr()
1265 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,  in emitAddSub_ri()
1310 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,  in emitAddSub_rs()
1347 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,  in emitAddSub_rx()
1387 bool AArch64FastISel::emitCmp(const Value *LHS, const Value *RHS, bool IsZExt) {  in emitCmp()
1409 bool AArch64FastISel::emitICmp(MVT RetVT, const Value *LHS, const Value *RHS,  in emitICmp()
1415 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,  in emitICmp_ri()
1421 bool AArch64FastISel::emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS) {  in emitFCmp()
1456 unsigned AArch64FastISel::emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,  in emitAdd()
1467 unsigned AArch64FastISel::emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill,  in emitAdd_ri_()
1486 unsigned AArch64FastISel::emitSub(MVT RetVT, const Value *LHS, const Value *RHS,  in emitSub()
1492 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg,  in emitSubs_rr()
1499 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg,  in emitSubs_rs()
1509 unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,  in emitLogicalOp()
1587 unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,  in emitLogicalOp_ri()
1633 unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT,  in emitLogicalOp_rs()
1671 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,  in emitAnd_ri()
1676 unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr,  in emitLoad()
1810 bool AArch64FastISel::selectAddSub(const Instruction *I) {  in selectAddSub()
1836 bool AArch64FastISel::selectLogicalOp(const Instruction *I) {  in selectLogicalOp()
1865 bool AArch64FastISel::selectLoad(const Instruction *I) {  in selectLoad()
1960 bool AArch64FastISel::emitStore(MVT VT, unsigned SrcReg, Address Addr,  in emitStore()
2025 bool AArch64FastISel::selectStore(const Instruction *I) {  in selectStore()
2111 bool AArch64FastISel::emitCompareAndBranch(const BranchInst *BI) {  in emitCompareAndBranch()
2238 bool AArch64FastISel::selectBranch(const Instruction *I) {  in selectBranch()
2427 bool AArch64FastISel::selectIndirectBr(const Instruction *I) {  in selectIndirectBr()
2445 bool AArch64FastISel::selectCmp(const Instruction *I) {  in selectCmp()
2527 bool AArch64FastISel::optimizeSelect(const SelectInst *SI) {  in optimizeSelect()
2582 bool AArch64FastISel::selectSelect(const Instruction *I) {  in selectSelect()
2709 bool AArch64FastISel::selectFPExt(const Instruction *I) {  in selectFPExt()
2725 bool AArch64FastISel::selectFPTrunc(const Instruction *I) {  in selectFPTrunc()
2742 bool AArch64FastISel::selectFPToInt(const Instruction *I, bool Signed) {  in selectFPToInt()
2775 bool AArch64FastISel::selectIntToFP(const Instruction *I, bool Signed) {  in selectIntToFP()
2817 bool AArch64FastISel::fastLowerArguments() {  in fastLowerArguments()
2926 bool AArch64FastISel::processCallArgs(CallLoweringInfo &CLI,  in processCallArgs()
3017 bool AArch64FastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,  in finishCall()
3056 bool AArch64FastISel::fastLowerCall(CallLoweringInfo &CLI) {  in fastLowerCall()
3175 bool AArch64FastISel::isMemCpySmall(uint64_t Len, unsigned Alignment) {  in isMemCpySmall()
3182 bool AArch64FastISel::tryEmitSmallMemCpy(Address Dest, Address Src,  in tryEmitSmallMemCpy()
3236 bool AArch64FastISel::foldXALUIntrinsic(AArch64CC::CondCode &CC,  in foldXALUIntrinsic()
3325 bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {  in fastLowerIntrinsicCall()
3656 bool AArch64FastISel::selectRet(const Instruction *I) {  in selectRet()
3750 bool AArch64FastISel::selectTrunc(const Instruction *I) {  in selectTrunc()
3816 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {  in emiti1Ext()
3849 unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,  in emitMul_rr()
3869 unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,  in emitSMULL_rr()
3879 unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,  in emitUMULL_rr()
3889 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,  in emitLSL_rr()
3915 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,  in emitLSL_ri()
3995 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,  in emitLSR_rr()
4022 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,  in emitLSR_ri()
4116 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,  in emitASR_rr()
4143 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,  in emitASR_ri()
4225 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,  in emitIntExt()
4334 bool AArch64FastISel::optimizeIntExtLoad(const Instruction *I, MVT RetVT,  in optimizeIntExtLoad()
4387 bool AArch64FastISel::selectIntExt(const Instruction *I) {  in selectIntExt()
4441 bool AArch64FastISel::selectRem(const Instruction *I, unsigned ISDOpcode) {  in selectRem()
4487 bool AArch64FastISel::selectMul(const Instruction *I) {  in selectMul()
4560 bool AArch64FastISel::selectShift(const Instruction *I) {  in selectShift()
4649 bool AArch64FastISel::selectBitCast(const Instruction *I) {  in selectBitCast()
4690 bool AArch64FastISel::selectFRem(const Instruction *I) {  in selectFRem()
4727 bool AArch64FastISel::selectSDiv(const Instruction *I) {  in selectSDiv()
4798 std::pair<unsigned, bool> AArch64FastISel::getRegForGEPIndex(const Value *Idx) {  in getRegForGEPIndex()
4821 bool AArch64FastISel::selectGetElementPtr(const Instruction *I) {  in selectGetElementPtr()
4890 bool AArch64FastISel::fastSelectInstruction(const Instruction *I) {  in fastSelectInstruction()
4974   return new AArch64FastISel(FuncInfo, LibInfo);  in createFastISel()