162                          bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
165                          bool LHSIsKill, uint64_t Imm, bool SetFlags = false,
168                          bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
173                          bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
182   bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
197   unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
199   unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
206                             bool LHSIsKill, uint64_t Imm);
208                             bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
210   unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
1131   bool LHSIsKill = hasTrivialKill(LHS);  in emitAddSub()  local
1140       ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm,  in emitAddSub()
1143       ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags,  in emitAddSub()
1147       ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, 0, SetFlags,  in emitAddSub()
1163           return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitAddSub()
1171     return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,  in emitAddSub()
1191       return emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,  in emitAddSub()
1212           return emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitAddSub()
1227   return emitAddSub_rr(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,  in emitAddSub()
1232                                         bool LHSIsKill, unsigned RHSReg,  in emitAddSub_rr()  argument
1260       .addReg(LHSReg, getKillRegState(LHSIsKill))  in emitAddSub_rr()
1266                                         bool LHSIsKill, uint64_t Imm,  in emitAddSub_ri()  argument
1304       .addReg(LHSReg, getKillRegState(LHSIsKill))  in emitAddSub_ri()
1311                                         bool LHSIsKill, unsigned RHSReg,  in emitAddSub_rs()  argument
1341       .addReg(LHSReg, getKillRegState(LHSIsKill))  in emitAddSub_rs()
1348                                         bool LHSIsKill, unsigned RHSReg,  in emitAddSub_rx()  argument
1381       .addReg(LHSReg, getKillRegState(LHSIsKill))  in emitAddSub_rx()
1415 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,  in emitICmp_ri()  argument
1417   return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, Imm,  in emitICmp_ri()
1435   bool LHSIsKill = hasTrivialKill(LHS);  in emitFCmp()  local
1440         .addReg(LHSReg, getKillRegState(LHSIsKill));  in emitFCmp()
1451       .addReg(LHSReg, getKillRegState(LHSIsKill))  in emitFCmp()
1493                                       bool LHSIsKill, unsigned RHSReg,  in emitSubs_rr()  argument
1495   return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitSubs_rr()
1500                                       bool LHSIsKill, unsigned RHSReg,  in emitSubs_rs()  argument
1504   return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitSubs_rs()
1529   bool LHSIsKill = hasTrivialKill(LHS);  in emitLogicalOp()  local
1534     ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm);  in emitLogicalOp()
1556       return emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitLogicalOp()
1569         return emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitLogicalOp()
1579   ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, LHSIsKill, RHSReg, RHSIsKill);  in emitLogicalOp()
1588                                            unsigned LHSReg, bool LHSIsKill,  in emitLogicalOp_ri()  argument
1624       fastEmitInst_ri(Opc, RC, LHSReg, LHSIsKill,  in emitLogicalOp_ri()
1634                                            unsigned LHSReg, bool LHSIsKill,  in emitLogicalOp_rs()  argument
1662       fastEmitInst_rri(Opc, RC, LHSReg, LHSIsKill, RHSReg, RHSIsKill,  in emitLogicalOp_rs()
1671 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,  in emitAnd_ri()  argument
1673   return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, LHSIsKill, Imm);  in emitAnd_ri()
3579       bool LHSIsKill = hasTrivialKill(LHS);  in fastLowerIntrinsicCall()  local
3587         MulReg = emitSMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);  in fastLowerIntrinsicCall()
3598         MulReg = emitMul_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);  in fastLowerIntrinsicCall()
3599         unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill,  in fastLowerIntrinsicCall()
3611       bool LHSIsKill = hasTrivialKill(LHS);  in fastLowerIntrinsicCall()  local
3619         MulReg = emitUMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);  in fastLowerIntrinsicCall()
3627         MulReg = emitMul_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);  in fastLowerIntrinsicCall()
3628         unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill,  in fastLowerIntrinsicCall()