193   unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm);
211   unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
213   unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
215   unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
217   unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
219   unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
221   unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
223   unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
225   unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
227   unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
1467 unsigned AArch64FastISel::emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill,  in emitAdd_ri_()  argument
1471     ResultReg = emitAddSub_ri(false, VT, Op0, Op0IsKill, -Imm);  in emitAdd_ri_()
1473     ResultReg = emitAddSub_ri(true, VT, Op0, Op0IsKill, Imm);  in emitAdd_ri_()
1482   ResultReg = emitAddSub_rr(true, VT, Op0, Op0IsKill, CReg, true);  in emitAdd_ri_()
3499     bool Op0IsKill = hasTrivialKill(II->getOperand(0));  in fastLowerIntrinsicCall()  local
3501     unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill);  in fastLowerIntrinsicCall()
3849 unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,  in emitMul_rr()  argument
3865   return fastEmitInst_rrr(Opc, RC, Op0, Op0IsKill, Op1, Op1IsKill,  in emitMul_rr()
3869 unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,  in emitSMULL_rr()  argument
3875                           Op0, Op0IsKill, Op1, Op1IsKill,  in emitSMULL_rr()
3879 unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,  in emitUMULL_rr()  argument
3885                           Op0, Op0IsKill, Op1, Op1IsKill,  in emitUMULL_rr()
3889 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,  in emitLSL_rr()  argument
3908   unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,  in emitLSL_rr()
3916                                      bool Op0IsKill, uint64_t Shift,  in emitLSL_ri()  argument
3939           .addReg(Op0, getKillRegState(Op0IsKill));  in emitLSL_ri()
3987         .addReg(Op0, getKillRegState(Op0IsKill))  in emitLSL_ri()
3990     Op0IsKill = true;  in emitLSL_ri()
3992   return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);  in emitLSL_ri()
3995 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,  in emitLSR_rr()  argument
4011     Op0Reg = emitAnd_ri(MVT::i32, Op0Reg, Op0IsKill, Mask);  in emitLSR_rr()
4013     Op0IsKill = Op1IsKill = true;  in emitLSR_rr()
4015   unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,  in emitLSR_rr()
4023                                      bool Op0IsKill, uint64_t Shift,  in emitLSR_ri()  argument
4046       .addReg(Op0, getKillRegState(Op0IsKill));  in emitLSR_ri()
4090     Op0IsKill = true;  in emitLSR_ri()
4108         .addReg(Op0, getKillRegState(Op0IsKill))  in emitLSR_ri()
4111     Op0IsKill = true;  in emitLSR_ri()
4113   return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);  in emitLSR_ri()
4116 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,  in emitASR_rr()  argument
4134     Op0IsKill = Op1IsKill = true;  in emitASR_rr()
4136   unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,  in emitASR_rr()
4144                                      bool Op0IsKill, uint64_t Shift,  in emitASR_ri()  argument
4167       .addReg(Op0, getKillRegState(Op0IsKill));  in emitASR_ri()
4217         .addReg(Op0, getKillRegState(Op0IsKill))  in emitASR_ri()
4220     Op0IsKill = true;  in emitASR_ri()
4222   return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);  in emitASR_ri()
4597     bool Op0IsKill = hasTrivialKill(Op0);  in selectShift()  local
4602       ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);  in selectShift()
4605       ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);  in selectShift()
4608       ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);  in selectShift()
4621   bool Op0IsKill = hasTrivialKill(I->getOperand(0));  in selectShift()  local
4632     ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);  in selectShift()
4635     ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);  in selectShift()
4638     ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);  in selectShift()
4680   bool Op0IsKill = hasTrivialKill(I->getOperand(0));  in selectBitCast()  local
4681   unsigned ResultReg = fastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill);  in selectBitCast()