Lines Matching refs:ResultReg
323 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); in fastMaterializeAlloca() local
325 ResultReg) in fastMaterializeAlloca()
329 return ResultReg; in fastMaterializeAlloca()
346 unsigned ResultReg = createResultReg(RC); in materializeInt() local
348 ResultReg).addReg(ZeroReg, getKillRegState(true)); in materializeInt()
349 return ResultReg; in materializeInt()
383 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP() local
385 TII.get(TargetOpcode::COPY), ResultReg) in materializeFP()
388 return ResultReg; in materializeFP()
403 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP() local
404 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in materializeFP()
407 return ResultReg; in materializeFP()
427 unsigned ResultReg; in materializeGV() local
435 ResultReg = createResultReg(&AArch64::GPR64RegClass); in materializeGV()
437 ResultReg) in materializeGV()
450 ResultReg = createResultReg(&AArch64::GPR64spRegClass); in materializeGV()
452 ResultReg) in materializeGV()
457 return ResultReg; in materializeGV()
980 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); in simplifyAddress() local
982 ResultReg) in simplifyAddress()
987 Addr.setReg(ResultReg); in simplifyAddress()
991 unsigned ResultReg = 0; in simplifyAddress() local
995 ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(), in simplifyAddress()
1000 ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(), in simplifyAddress()
1006 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(), in simplifyAddress()
1010 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(), in simplifyAddress()
1014 ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(), in simplifyAddress()
1017 if (!ResultReg) in simplifyAddress()
1020 Addr.setReg(ResultReg); in simplifyAddress()
1029 unsigned ResultReg; in simplifyAddress() local
1032 ResultReg = emitAdd_ri_(MVT::i64, Addr.getReg(), /*IsKill=*/false, Offset); in simplifyAddress()
1034 ResultReg = fastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset); in simplifyAddress()
1036 if (!ResultReg) in simplifyAddress()
1038 Addr.setReg(ResultReg); in simplifyAddress()
1136 unsigned ResultReg = 0; in emitAddSub() local
1140 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm, in emitAddSub()
1143 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags, in emitAddSub()
1147 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, 0, SetFlags, in emitAddSub()
1150 if (ResultReg) in emitAddSub()
1151 return ResultReg; in emitAddSub()
1250 unsigned ResultReg; in emitAddSub_rr() local
1252 ResultReg = createResultReg(RC); in emitAddSub_rr()
1254 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in emitAddSub_rr()
1259 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in emitAddSub_rr()
1262 return ResultReg; in emitAddSub_rr()
1295 unsigned ResultReg; in emitAddSub_ri() local
1297 ResultReg = createResultReg(RC); in emitAddSub_ri()
1299 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in emitAddSub_ri()
1303 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in emitAddSub_ri()
1307 return ResultReg; in emitAddSub_ri()
1331 unsigned ResultReg; in emitAddSub_rs() local
1333 ResultReg = createResultReg(RC); in emitAddSub_rs()
1335 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in emitAddSub_rs()
1340 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in emitAddSub_rs()
1344 return ResultReg; in emitAddSub_rs()
1371 unsigned ResultReg; in emitAddSub_rx() local
1373 ResultReg = createResultReg(RC); in emitAddSub_rx()
1375 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in emitAddSub_rx()
1380 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in emitAddSub_rx()
1384 return ResultReg; in emitAddSub_rx()
1469 unsigned ResultReg; in emitAdd_ri_() local
1471 ResultReg = emitAddSub_ri(false, VT, Op0, Op0IsKill, -Imm); in emitAdd_ri_()
1473 ResultReg = emitAddSub_ri(true, VT, Op0, Op0IsKill, Imm); in emitAdd_ri_()
1475 if (ResultReg) in emitAdd_ri_()
1476 return ResultReg; in emitAdd_ri_()
1482 ResultReg = emitAddSub_rr(true, VT, Op0, Op0IsKill, CReg, true); in emitAdd_ri_()
1483 return ResultReg; in emitAdd_ri_()
1531 unsigned ResultReg = 0; in emitLogicalOp() local
1534 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm); in emitLogicalOp()
1536 if (ResultReg) in emitLogicalOp()
1537 return ResultReg; in emitLogicalOp()
1579 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, LHSIsKill, RHSReg, RHSIsKill); in emitLogicalOp()
1582 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitLogicalOp()
1584 return ResultReg; in emitLogicalOp()
1623 unsigned ResultReg = in emitLogicalOp_ri() local
1628 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitLogicalOp_ri()
1630 return ResultReg; in emitLogicalOp_ri()
1661 unsigned ResultReg = in emitLogicalOp_rs() local
1666 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitLogicalOp_rs()
1668 return ResultReg; in emitLogicalOp_rs()
1784 unsigned ResultReg = createResultReg(RC); in emitLoad() local
1786 TII.get(Opc), ResultReg); in emitLoad()
1791 unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, 1); in emitLoad()
1793 ResultReg = ANDReg; in emitLoad()
1803 .addReg(ResultReg, getKillRegState(true)) in emitLoad()
1805 ResultReg = Reg64; in emitLoad()
1807 return ResultReg; in emitLoad()
1818 unsigned ResultReg; in selectAddSub() local
1823 ResultReg = emitAdd(VT, I->getOperand(0), I->getOperand(1)); in selectAddSub()
1826 ResultReg = emitSub(VT, I->getOperand(0), I->getOperand(1)); in selectAddSub()
1829 if (!ResultReg) in selectAddSub()
1832 updateValueMap(I, ResultReg); in selectAddSub()
1844 unsigned ResultReg; in selectLogicalOp() local
1849 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1)); in selectLogicalOp()
1852 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1)); in selectLogicalOp()
1855 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1)); in selectLogicalOp()
1858 if (!ResultReg) in selectLogicalOp()
1861 updateValueMap(I, ResultReg); in selectLogicalOp()
1898 unsigned ResultReg = in selectLoad() local
1900 if (!ResultReg) in selectLoad()
1926 ResultReg = std::prev(FuncInfo.InsertPt)->getOperand(0).getReg(); in selectLoad()
1928 ResultReg = fastEmitInst_extractsubreg(MVT::i32, ResultReg, in selectLoad()
1932 updateValueMap(I, ResultReg); in selectLoad()
1952 updateValueMap(IntExtVal, ResultReg); in selectLoad()
1956 updateValueMap(I, ResultReg); in selectLoad()
2450 unsigned ResultReg = 0; in selectCmp() local
2455 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectCmp()
2457 TII.get(TargetOpcode::COPY), ResultReg) in selectCmp()
2461 ResultReg = fastEmit_i(MVT::i32, MVT::i32, ISD::Constant, 1); in selectCmp()
2465 if (ResultReg) { in selectCmp()
2466 updateValueMap(I, ResultReg); in selectCmp()
2474 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectCmp()
2502 ResultReg) in selectCmp()
2507 updateValueMap(I, ResultReg); in selectCmp()
2516 ResultReg) in selectCmp()
2521 updateValueMap(I, ResultReg); in selectCmp()
2576 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32spRegClass, Src1Reg, in optimizeSelect() local
2578 updateValueMap(SI, ResultReg); in optimizeSelect()
2703 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect() local
2705 updateValueMap(I, ResultReg); in selectSelect()
2718 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass); in selectFPExt() local
2720 ResultReg).addReg(Op); in selectFPExt()
2721 updateValueMap(I, ResultReg); in selectFPExt()
2734 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass); in selectFPTrunc() local
2736 ResultReg).addReg(Op); in selectFPTrunc()
2737 updateValueMap(I, ResultReg); in selectFPTrunc()
2767 unsigned ResultReg = createResultReg( in selectFPToInt() local
2769 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in selectFPToInt()
2771 updateValueMap(I, ResultReg); in selectFPToInt()
2811 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg, in selectIntToFP() local
2813 updateValueMap(I, ResultReg); in selectIntToFP()
2917 unsigned ResultReg = createResultReg(RC); in fastLowerArguments() local
2919 TII.get(TargetOpcode::COPY), ResultReg) in fastLowerArguments()
2921 updateValueMap(&Arg, ResultReg); in fastLowerArguments()
3043 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); in finishCall() local
3045 TII.get(TargetOpcode::COPY), ResultReg) in finishCall()
3049 CLI.ResultReg = ResultReg; in finishCall()
3215 unsigned ResultReg = emitLoad(VT, VT, Src); in tryEmitSmallMemCpy() local
3216 if (!ResultReg) in tryEmitSmallMemCpy()
3219 if (!emitStore(VT, ResultReg, Dest)) in tryEmitSmallMemCpy()
3455 updateValueMap(II, CLI.ResultReg); in fastLowerIntrinsicCall()
3478 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall() local
3479 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastLowerIntrinsicCall()
3481 updateValueMap(II, ResultReg); in fastLowerIntrinsicCall()
3501 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill); in fastLowerIntrinsicCall() local
3502 if (!ResultReg) in fastLowerIntrinsicCall()
3505 updateValueMap(II, ResultReg); in fastLowerIntrinsicCall()
3782 unsigned ResultReg; in selectTrunc() local
3803 ResultReg = emitAnd_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask); in selectTrunc()
3804 assert(ResultReg && "Unexpected AND instruction emission failure."); in selectTrunc()
3806 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectTrunc()
3808 TII.get(TargetOpcode::COPY), ResultReg) in selectTrunc()
3812 updateValueMap(I, ResultReg); in selectTrunc()
3825 unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1); in emiti1Ext() local
3826 assert(ResultReg && "Unexpected AND instruction emission failure."); in emiti1Ext()
3834 .addReg(ResultReg) in emiti1Ext()
3836 ResultReg = Reg64; in emiti1Ext()
3838 return ResultReg; in emiti1Ext()
3908 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitLSL_rr() local
3911 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitLSL_rr()
3912 return ResultReg; in emitLSL_rr()
3936 unsigned ResultReg = createResultReg(RC); in emitLSL_ri() local
3938 TII.get(TargetOpcode::COPY), ResultReg) in emitLSL_ri()
3940 return ResultReg; in emitLSL_ri()
4015 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitLSR_rr() local
4018 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitLSR_rr()
4019 return ResultReg; in emitLSR_rr()
4043 unsigned ResultReg = createResultReg(RC); in emitLSR_ri() local
4045 TII.get(TargetOpcode::COPY), ResultReg) in emitLSR_ri()
4047 return ResultReg; in emitLSR_ri()
4136 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitASR_rr() local
4139 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitASR_rr()
4140 return ResultReg; in emitASR_rr()
4164 unsigned ResultReg = createResultReg(RC); in emitASR_ri() local
4166 TII.get(TargetOpcode::COPY), ResultReg) in emitASR_ri()
4168 return ResultReg; in emitASR_ri()
4412 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass); in selectIntExt() local
4414 TII.get(AArch64::SUBREG_TO_REG), ResultReg) in selectIntExt()
4418 SrcReg = ResultReg; in selectIntExt()
4433 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt); in selectIntExt() local
4434 if (!ResultReg) in selectIntExt()
4437 updateValueMap(I, ResultReg); in selectIntExt()
4480 unsigned ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, /*IsKill=*/true, in selectRem() local
4483 updateValueMap(I, ResultReg); in selectRem()
4532 unsigned ResultReg = in selectMul() local
4535 if (ResultReg) { in selectMul()
4536 updateValueMap(I, ResultReg); in selectMul()
4551 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill); in selectMul() local
4553 if (!ResultReg) in selectMul()
4556 updateValueMap(I, ResultReg); in selectMul()
4569 unsigned ResultReg = 0; in selectShift() local
4602 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4605 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4608 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4611 if (!ResultReg) in selectShift()
4614 updateValueMap(I, ResultReg); in selectShift()
4628 unsigned ResultReg = 0; in selectShift() local
4632 ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill); in selectShift()
4635 ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill); in selectShift()
4638 ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill); in selectShift()
4642 if (!ResultReg) in selectShift()
4645 updateValueMap(I, ResultReg); in selectShift()
4681 unsigned ResultReg = fastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill); in selectBitCast() local
4683 if (!ResultReg) in selectBitCast()
4686 updateValueMap(I, ResultReg); in selectBitCast()
4723 updateValueMap(I, CLI.ResultReg); in selectFRem()
4747 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2); in selectSDiv() local
4748 if (!ResultReg) in selectSDiv()
4750 updateValueMap(I, ResultReg); in selectSDiv()
4781 unsigned ResultReg; in selectSDiv() local
4783 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, /*IsKill=*/true, in selectSDiv()
4786 ResultReg = emitASR_ri(VT, VT, SelectReg, /*IsKill=*/true, Lg2); in selectSDiv()
4788 if (!ResultReg) in selectSDiv()
4791 updateValueMap(I, ResultReg); in selectSDiv()