897 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) {  in createDTuple()  argument
903   return createTuple(Regs, RegClassIDs, SubRegs);  in createDTuple()
906 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) {  in createQTuple()  argument
912   return createTuple(Regs, RegClassIDs, SubRegs);  in createQTuple()
915 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs,  in createTuple()  argument
920   if (Regs.size() == 1)  in createTuple()
921     return Regs[0];  in createTuple()
923   assert(Regs.size() >= 2 && Regs.size() <= 4);  in createTuple()
925   SDLoc DL(Regs[0].getNode());  in createTuple()
931       CurDAG->getTargetConstant(RegClassIDs[Regs.size() - 2], MVT::i32));  in createTuple()
934   for (unsigned i = 0; i < Regs.size(); ++i) {  in createTuple()
935     Ops.push_back(Regs[i]);  in createTuple()
953   SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off,  in SelectTable()  local
955   SDValue RegSeq = createQTuple(Regs);  in SelectTable()
1116   SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);  in SelectStore()  local
1117   SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);  in SelectStore()
1134   SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);  in SelectPostStore()  local
1135   SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);  in SelectPostStore()
1188   SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);  in SelectLoadLane()  local
1191     std::transform(Regs.begin(), Regs.end(), Regs.begin(),  in SelectLoadLane()
1194   SDValue RegSeq = createQTuple(Regs);  in SelectLoadLane()
1228   SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);  in SelectPostLoadLane()  local
1231     std::transform(Regs.begin(), Regs.end(), Regs.begin(),  in SelectPostLoadLane()
1234   SDValue RegSeq = createQTuple(Regs);  in SelectPostLoadLane()
1283   SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);  in SelectStoreLane()  local
1286     std::transform(Regs.begin(), Regs.end(), Regs.begin(),  in SelectStoreLane()
1289   SDValue RegSeq = createQTuple(Regs);  in SelectStoreLane()
1313   SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);  in SelectPostStoreLane()  local
1316     std::transform(Regs.begin(), Regs.end(), Regs.begin(),  in SelectPostStoreLane()
1319   SDValue RegSeq = createQTuple(Regs);  in SelectPostStoreLane()