78 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,  in AArch64TargetLowering()  function in AArch64TargetLowering
621 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {  in addTypeForNEON()
690 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {  in addDRTypeForNEON()
695 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {  in addQRTypeForNEON()
700 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {  in getSetCCResultType()
709 void AArch64TargetLowering::computeKnownBitsForTargetNode(  in computeKnownBitsForTargetNode()
769 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {  in getScalarShiftAmountTy()
774 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,  in createFastISel()
779 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {  in getTargetNodeName()
905 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,  in EmitF128CSEL()
966 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,  in EmitInstrWithCustomInserter()
1377 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,  in LowerF128Call()
1535 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,  in LowerFP_EXTEND()
1545 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,  in LowerFP_ROUND()
1591 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,  in LowerFP_TO_INT()
1648 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,  in LowerINT_TO_FP()
1680 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,  in LowerFSINCOS()
1918 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,  in LowerOperation()
2023 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {  in getFunctionAlignment()
2034 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,  in CCAssignFnForCall()
2051 SDValue AArch64TargetLowering::LowerFormalArguments(  in LowerFormalArguments()
2249 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,  in saveVarArgRegisters()
2322 SDValue AArch64TargetLowering::LowerCallResult(  in LowerCallResult()
2370 bool AArch64TargetLowering::isEligibleForTailCallOptimization(  in isEligibleForTailCallOptimization()
2490 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,  in addTokenForArgument()
2523 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,  in DoesCalleeRestoreStack()
2528 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {  in IsTailCallConvention()
2535 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,  in LowerCall()
2893 bool AArch64TargetLowering::CanLowerReturn(  in CanLowerReturn()
2905 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,  in LowerReturn()
2962 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,  in LowerGlobalAddress()
3051 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,  in LowerDarwinGlobalTLSAddress()
3109 SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,  in LowerELFTLSDescCallSeq()
3127 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,  in LowerELFGlobalTLSAddress()
3221 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,  in LowerGlobalTLSAddress()
3230 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {  in LowerBR_CC()
3360 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,  in LowerFCOPYSIGN()
3440 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {  in LowerCTPOP()
3474 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {  in LowerSETCC()
3571 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,  in LowerSELECT_CC()
3750 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,  in LowerSELECT_CC()
3761 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,  in LowerSELECT()
3802 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,  in LowerJumpTable()
3830 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,  in LowerConstantPool()
3871 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,  in LowerBlockAddress()
3894 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,  in LowerDarwin_VASTART()
3907 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,  in LowerAAPCS_VASTART()
3974 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,  in LowerVASTART()
3980 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,  in LowerVACOPY()
3994 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {  in LowerVAARG()
4056 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,  in LowerFRAMEADDR()
4074 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,  in getRegisterByName()
4084 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,  in LowerRETURNADDR()
4108 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,  in LowerShiftRightParts()
4154 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,  in LowerShiftLeftParts()
4193 bool AArch64TargetLowering::isOffsetFoldingLegal(  in isOffsetFoldingLegal()
4199 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {  in isFPImmLegal()
4246 AArch64TargetLowering::ConstraintType
4247 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {  in getConstraintType()
4270 AArch64TargetLowering::getSingleConstraintMatchWeight(  in getSingleConstraintMatchWeight()
4297 AArch64TargetLowering::getRegForInlineAsmConstraint(  in getRegForInlineAsmConstraint()
4353 void AArch64TargetLowering::LowerAsmOperandForConstraint(  in LowerAsmOperandForConstraint()
4527 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,  in ReconstructShuffle()
5176 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,  in LowerVECTOR_SHUFFLE()
5353 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,  in LowerVectorAND()
5544 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,  in LowerVectorOR()
5671 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,  in LowerBUILD_VECTOR()
6045 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,  in LowerINSERT_VECTOR_ELT()
6079 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,  in LowerEXTRACT_VECTOR_ELT()
6115 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,  in LowerEXTRACT_SUBVECTOR()
6155 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,  in isShuffleMaskLegal()
6242 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,  in LowerVectorSRA_SRL_SHL()
6385 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,  in LowerVSETCC()
6436 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,  in getTgtMemIntrinsic()
6549 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {  in isTruncateFree()
6556 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {  in isTruncateFree()
6567 bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {  in isProfitableToHoist()
6594 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {  in isZExtFree()
6601 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {  in isZExtFree()
6609 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {  in isZExtFree()
6624 bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {  in isExtFreeImpl()
6677 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,  in hasPairedLoad()
6687 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,  in hasPairedLoad()
6704 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,  in getOptimalMemOpType()
6734 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {  in isLegalAddImmediate()
6742 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {  in isLegalICmpImmediate()
6750 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,  in isLegalAddressingMode()
6801 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,  in getScalingFactorCost()
6817 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {  in isFMAFasterThanFMulAndFAdd()
6835 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {  in getScratchRegisters()
6846 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {  in isDesirableToCommuteWithShift()
6861 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,  in shouldConvertConstantLoadToIntImm()
6923 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,  in BuildSDIVPow2()
8682 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,  in PerformDAGCombine()
8760 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,  in isUsedByReturnOnly()
8797 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {  in mayBeEmittedAsTailCall()
8804 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,  in getIndexedAddressParts()
8826 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,  in getPreIndexedAddressParts()
8848 bool AArch64TargetLowering::getPostIndexedAddressParts(  in getPostIndexedAddressParts()
8890 void AArch64TargetLowering::ReplaceNodeResults(  in ReplaceNodeResults()
8906 bool AArch64TargetLowering::useLoadStackGuardNode() const {  in useLoadStackGuardNode()
8910 bool AArch64TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {  in combineRepeatedFPDivisors()
8917 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {  in getPreferredVectorAction()
8931 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {  in shouldExpandAtomicStoreInIR()
8939 bool AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {  in shouldExpandAtomicLoadInIR()
8946 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {  in shouldExpandAtomicRMWInIR()
8952 bool AArch64TargetLowering::hasLoadLinkedStoreConditional() const {  in hasLoadLinkedStoreConditional()
8956 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,  in emitLoadLinked()
8991 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,  in emitStoreConditional()
9023 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(  in functionArgumentNeedsConsecutiveRegisters()