1429     SDValue CCVal;  in LowerXOR()  local
1430     SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);  in LowerXOR()
1437                        CCVal, Cmp);  in LowerXOR()
1496   SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32);  in LowerXALUO()  local
1498                          CCVal, Overflow);  in LowerXALUO()
3272     SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);  in LowerBR_CC()  local
3274     return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,  in LowerBR_CC()
3335     SDValue CCVal;  in LowerBR_CC()  local
3336     SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);  in LowerBR_CC()
3337     return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,  in LowerBR_CC()
3503     SDValue CCVal;  in LowerSETCC()  local
3505         getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);  in LowerSETCC()
3510     return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);  in LowerSETCC()
3679     SDValue CCVal;  in LowerSELECT_CC()  local
3680     SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);  in LowerSELECT_CC()
3683     return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);  in LowerSELECT_CC()
3763   SDValue CCVal = Op->getOperand(0);  in LowerSELECT()  local
3768   unsigned Opc = CCVal.getOpcode();  in LowerSELECT()
3771   if (CCVal.getResNo() == 1 &&  in LowerSELECT()
3775     if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0)))  in LowerSELECT()
3780     std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG);  in LowerSELECT()
3781     SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);  in LowerSELECT()  local
3784                        CCVal, Overflow);  in LowerSELECT()
3790   if (CCVal.getOpcode() == ISD::SETCC) {  in LowerSELECT()
3791     LHS = CCVal.getOperand(0);  in LowerSELECT()
3792     RHS = CCVal.getOperand(1);  in LowerSELECT()
3793     CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();  in LowerSELECT()
3795     LHS = CCVal;  in LowerSELECT()
3796     RHS = DAG.getConstant(0, CCVal.getValueType());  in LowerSELECT()
4131   SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);  in LowerShiftRightParts()  local
4136       DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);  in LowerShiftRightParts()
4146       DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);  in LowerShiftRightParts()
4178   SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);  in LowerShiftLeftParts()  local
4180       DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);  in LowerShiftLeftParts()
4187       DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);  in LowerShiftLeftParts()
6939   SDValue CCVal;  in BuildSDIVPow2()  local
6940   SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);  in BuildSDIVPow2()
6942   SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);  in BuildSDIVPow2()
7603   SDValue CCVal;  in performSetccAddFolding()  local
7607     CCVal = DAG.getConstant(  in performSetccAddFolding()
7614                       CCVal, DAG, dl);  in performSetccAddFolding()
7618   return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);  in performSetccAddFolding()
8558   SDValue CCVal = N->getOperand(2);  in performBRCONDCombine()  local
8561   assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");  in performBRCONDCombine()
8562   unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();  in performBRCONDCombine()