Lines Matching refs:VTs
1326 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32); in getAArch64XALUOOp() local
1327 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits) in getAArch64XALUOOp()
1337 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32); in getAArch64XALUOOp() local
1339 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64), in getAArch64XALUOOp()
1353 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32); in getAArch64XALUOOp() local
1354 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits) in getAArch64XALUOOp()
1358 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32); in getAArch64XALUOOp() local
1360 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64), in getAArch64XALUOOp()
1368 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32); in getAArch64XALUOOp() local
1371 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS); in getAArch64XALUOOp()
1450 SDVTList VTs = DAG.getVTList(VT, MVT::i32); in LowerADDC_ADDE_SUBC_SUBE() local
1474 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1)); in LowerADDC_ADDE_SUBC_SUBE()
1475 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1), in LowerADDC_ADDE_SUBC_SUBE()
1500 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); in LowerXALUO() local
1501 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow); in LowerXALUO()
8539 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0), in performCONDCombine() local
8543 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops); in performCONDCombine()