4821 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isZIPMask()  argument
4823   WhichResult = (M[0] == 0 ? 0 : 1);  in isZIPMask()
4824   unsigned Idx = WhichResult * NumElts / 2;  in isZIPMask()
4835 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isUZPMask()  argument
4837   WhichResult = (M[0] == 0 ? 0 : 1);  in isUZPMask()
4841     if ((unsigned)M[i] != 2 * i + WhichResult)  in isUZPMask()
4848 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isTRNMask()  argument
4850   WhichResult = (M[0] == 0 ? 0 : 1);  in isTRNMask()
4852     if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||  in isTRNMask()
4853         (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))  in isTRNMask()
4862 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isZIP_v_undef_Mask()  argument
4864   WhichResult = (M[0] == 0 ? 0 : 1);  in isZIP_v_undef_Mask()
4865   unsigned Idx = WhichResult * NumElts / 2;  in isZIP_v_undef_Mask()
4879 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isUZP_v_undef_Mask()  argument
4881   WhichResult = (M[0] == 0 ? 0 : 1);  in isUZP_v_undef_Mask()
4883     unsigned Idx = WhichResult;  in isUZP_v_undef_Mask()
4898 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isTRN_v_undef_Mask()  argument
4900   WhichResult = (M[0] == 0 ? 0 : 1);  in isTRN_v_undef_Mask()
4902     if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||  in isTRN_v_undef_Mask()
4903         (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))  in isTRN_v_undef_Mask()
5249   unsigned WhichResult;  in LowerVECTOR_SHUFFLE()  local
5250   if (isZIPMask(ShuffleMask, VT, WhichResult)) {  in LowerVECTOR_SHUFFLE()
5251     unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;  in LowerVECTOR_SHUFFLE()
5254   if (isUZPMask(ShuffleMask, VT, WhichResult)) {  in LowerVECTOR_SHUFFLE()
5255     unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;  in LowerVECTOR_SHUFFLE()
5258   if (isTRNMask(ShuffleMask, VT, WhichResult)) {  in LowerVECTOR_SHUFFLE()
5259     unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;  in LowerVECTOR_SHUFFLE()
5263   if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {  in LowerVECTOR_SHUFFLE()
5264     unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;  in LowerVECTOR_SHUFFLE()
5267   if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {  in LowerVECTOR_SHUFFLE()
5268     unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;  in LowerVECTOR_SHUFFLE()
5271   if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {  in LowerVECTOR_SHUFFLE()
5272     unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;  in LowerVECTOR_SHUFFLE()