Lines Matching refs:Offset64
7798 int Offset64, bits<4> opcode> {
7847 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7852 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7857 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7864 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
7865 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
7866 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
7871 int Offset64, bits<4> opcode> {
7919 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7924 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7929 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7936 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
7937 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
7938 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
7942 int Offset128, int Offset64, bits<4> opcode>
7943 : BaseSIMDLdN<Count, asm, veclist, Offset128, Offset64, opcode> {
7955 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7958 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
7962 int Offset128, int Offset64, bits<4> opcode>
7963 : BaseSIMDStN<Count, asm, veclist, Offset128, Offset64, opcode> {
7975 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7978 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;