Lines Matching refs:Rn
966 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
967 bits<5> Rn;
968 let Inst{9-5} = Rn;
1130 def : Pat<(node GPR64:$Rn, tbz_imm0_31_diag:$imm, bb:$target),
1131 (!cast<Instruction>(NAME#"W") (EXTRACT_SUBREG GPR64:$Rn, sub_32),
1175 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
1176 [(set regtype:$Rd, (node regtype:$Rn))]>,
1179 bits<5> Rn;
1183 let Inst{9-5} = Rn;
1214 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1215 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1219 bits<5> Rn;
1225 let Inst{9-5} = Rn;
1232 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1237 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1268 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1269 asm, "\t$Rd, $Rn, $Rm", "",
1270 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]> {
1272 bits<5> Rn;
1278 let Inst{9-5} = Rn;
1315 def : Pat<(i32 (OpNode GPR32:$Rn, i64:$Rm)),
1316 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn,
1319 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (zext GPR32:$Rm)))),
1320 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1322 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (anyext GPR32:$Rm)))),
1323 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1325 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (sext GPR32:$Rm)))),
1326 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1336 : I<(outs addtype:$Rd), (ins multype:$Rn, multype:$Rm, addtype:$Ra),
1337 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pattern> {
1339 bits<5> Rn;
1347 let Inst{9-5} = Rn;
1354 [/*(set GPR32:$Rd, (AccNode GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm)))*/]>,
1360 [/*(set GPR64:$Rd, (AccNode GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm)))*/]>,
1370 (mul (ExtNode GPR32:$Rn), (ExtNode GPR32:$Rm))))]>,
1376 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
1377 asm, "\t$Rd, $Rn, $Rm", "",
1378 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64:$Rm))]>,
1381 bits<5> Rn;
1387 let Inst{9-5} = Rn;
1407 : I<(outs GPR32:$Rd), (ins GPR32:$Rn, StreamReg:$Rm),
1408 asm, "\t$Rd, $Rn, $Rm", "",
1409 [(set GPR32:$Rd, (OpNode GPR32:$Rn, StreamReg:$Rm))]>,
1412 bits<5> Rn;
1421 let Inst{9-5} = Rn;
1527 : I<(outs dstRegtype:$Rd), (ins srcRegtype:$Rn, immtype:$imm),
1528 asm, "\t$Rd, $Rn, $imm", "",
1529 [(set dstRegtype:$Rd, (OpNode srcRegtype:$Rn, immtype:$imm))]>,
1532 bits<5> Rn;
1539 let Inst{9-5} = Rn;
1546 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1547 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
1553 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1554 asm, "\t$Rd, $Rn, $Rm", "",
1555 [(set regtype:$Rd, (OpNode regtype:$Rn, shifted_regtype:$Rm))]>,
1587 bits<5> Rn;
1597 let Inst{9-5} = Rn;
1608 (ins src1Regtype:$Rn, src2Regtype:$Rm, ext_op:$ext),
1609 asm, "\t$Rd, $Rn, $Rm$ext", "", []>,
1612 bits<5> Rn;
1622 let Inst{9-5} = Rn;
1805 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, imm_type:$imm),
1806 asm, "\t$Rd, $Rn, $Rm, $imm", "", patterns>,
1809 bits<5> Rn;
1817 let Inst{9-5} = Rn;
1824 (AArch64Extr GPR32:$Rn, GPR32:$Rm, imm0_31:$imm))]> {
1832 (AArch64Extr GPR64:$Rn, GPR64:$Rm, imm0_63:$imm))]> {
1846 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
1847 asm, "\t$Rd, $Rn, $immr, $imms", "", []>,
1850 bits<5> Rn;
1858 let Inst{9-5} = Rn;
1879 : I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr,
1881 asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>,
1884 bits<5> Rn;
1892 let Inst{9-5} = Rn;
1918 : I<(outs dregtype:$Rd), (ins sregtype:$Rn, imm_type:$imm),
1919 asm, "\t$Rd, $Rn, $imm", "", pattern>,
1922 bits<5> Rn;
1929 let Inst{9-5} = Rn;
1939 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1940 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1971 [(set GPR32sp:$Rd, (OpNode GPR32:$Rn,
1978 [(set GPR64sp:$Rd, (OpNode GPR64:$Rn,
1983 def : InstAlias<Alias # " $Rd, $Rn, $imm",
1984 (!cast<Instruction>(NAME # "Wri") GPR32sp:$Rd, GPR32:$Rn,
1986 def : InstAlias<Alias # " $Rd, $Rn, $imm",
1987 (!cast<Instruction>(NAME # "Xri") GPR64sp:$Rd, GPR64:$Rn,
1995 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_imm32:$imm))]> {
2000 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_imm64:$imm))]> {
2005 def : InstAlias<Alias # " $Rd, $Rn, $imm",
2006 (!cast<Instruction>(NAME # "Wri") GPR32:$Rd, GPR32:$Rn,
2008 def : InstAlias<Alias # " $Rd, $Rn, $imm",
2009 (!cast<Instruction>(NAME # "Xri") GPR64:$Rd, GPR64:$Rn,
2014 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
2015 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
2027 [(set GPR32:$Rd, (OpNode GPR32:$Rn,
2032 [(set GPR64:$Rd, (OpNode GPR64:$Rn,
2051 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_shifted_reg32:$Rm))]> {
2055 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_shifted_reg64:$Rm))]> {
2072 : I<(outs), (ins regtype:$Rn, imm0_31:$imm, imm0_15:$nzcv, ccode:$cond),
2073 asm, "\t$Rn, $imm, $nzcv, $cond", "", []>,
2078 bits<5> Rn;
2088 let Inst{9-5} = Rn;
2104 : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
2105 asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
2110 bits<5> Rn;
2120 let Inst{9-5} = Rn;
2139 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2140 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2142 (AArch64csel regtype:$Rn, regtype:$Rm, (i32 imm:$cond), NZCV))]>,
2147 bits<5> Rn;
2156 let Inst{9-5} = Rn;
2171 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2172 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2174 (AArch64csel regtype:$Rn, (frag regtype:$Rm),
2180 bits<5> Rn;
2189 let Inst{9-5} = Rn;
2206 def : Pat<(AArch64csel (frag GPR32:$Rm), GPR32:$Rn, (i32 imm:$cond), NZCV),
2207 (!cast<Instruction>(NAME # Wr) GPR32:$Rn, GPR32:$Rm,
2210 def : Pat<(AArch64csel (frag GPR64:$Rm), GPR64:$Rn, (i32 imm:$cond), NZCV),
2211 (!cast<Instruction>(NAME # Xr) GPR64:$Rn, GPR64:$Rm,
2267 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
2270 bits<5> Rn;
2279 let Inst{9-5} = Rn;
2289 (ins GPR64sp:$Rn, indextype:$offset),
2293 def : InstAlias<asm # " $Rt, [$Rn]",
2294 (!cast<Instruction>(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>;
2301 (ins regtype:$Rt, GPR64sp:$Rn, indextype:$offset),
2305 def : InstAlias<asm # " $Rt, [$Rn]",
2306 (!cast<Instruction>(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>;
2321 (outs), (ins prfop:$Rt, GPR64sp:$Rn, uimm12s8:$offset),
2452 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2454 bits<5> Rn;
2468 let Inst{9-5} = Rn;
2473 : InstAlias<asm # " $Rt, [$Rn, $Rm]",
2474 (INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
2481 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend),
2483 (loadop (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
2492 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
2494 (loadop (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
2507 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend),
2509 (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
2517 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
2519 (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
2530 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2532 bits<5> Rn;
2546 let Inst{9-5} = Rn;
2554 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend),
2556 (loadop (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2564 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend),
2566 (loadop (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2579 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend),
2581 (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2589 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend),
2591 (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2602 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2604 bits<5> Rn;
2618 let Inst{9-5} = Rn;
2626 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend),
2628 (loadop (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
2636 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend),
2638 (loadop (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
2651 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend),
2653 (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
2661 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend),
2663 (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
2674 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2676 bits<5> Rn;
2690 let Inst{9-5} = Rn;
2698 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2700 (loadop (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2708 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2710 (loadop (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2723 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2725 (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2733 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2735 (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2746 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2748 bits<5> Rn;
2762 let Inst{9-5} = Rn;
2770 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend),
2772 (loadop (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
2780 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend),
2782 (loadop (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
2795 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend),
2797 (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
2805 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend),
2807 (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
2819 : I<outs, ins, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat>,
2822 bits<5> Rn;
2836 let Inst{9-5} = Rn;
2842 (ins prfop:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2844 (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2850 (ins prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2852 (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2857 def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
2859 GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
2874 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
2876 bits<5> Rn;
2886 let Inst{9-5} = Rn;
2896 (ins GPR64sp:$Rn, simm9:$offset), asm, pattern>,
2899 def : InstAlias<asm # " $Rt, [$Rn]",
2900 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2907 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
2911 def : InstAlias<asm # " $Rt, [$Rn]",
2912 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2919 (ins prfop:$Rt, GPR64sp:$Rn, simm9:$offset),
2923 def : InstAlias<asm # " $Rt, [$Rn]",
2924 (!cast<Instruction>(NAME # "i") prfop:$Rt, GPR64sp:$Rn, 0)>;
2933 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", []> {
2935 bits<5> Rn;
2945 let Inst{9-5} = Rn;
2955 (ins GPR64sp:$Rn, simm9:$offset), asm>,
2958 def : InstAlias<asm # " $Rt, [$Rn]",
2959 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2966 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
2970 def : InstAlias<asm # " $Rt, [$Rn]",
2971 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2980 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]!", cstr, pat> {
2982 bits<5> Rn;
2992 let Inst{9-5} = Rn;
3004 (ins GPR64sp:$Rn, simm9:$offset), asm,
3005 "$Rn = $wback,@earlyclobber $wback", []>,
3013 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
3014 asm, "$Rn = $wback,@earlyclobber $wback",
3016 (storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
3026 : I<oops, iops, asm, "\t$Rt, [$Rn], $offset", cstr, pat> {
3028 bits<5> Rn;
3038 let Inst{9-5} = Rn;
3050 (ins GPR64sp:$Rn, simm9:$offset),
3051 asm, "$Rn = $wback,@earlyclobber $wback", []>,
3059 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
3060 asm, "$Rn = $wback,@earlyclobber $wback",
3062 (storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
3075 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
3078 bits<5> Rn;
3087 let Inst{9-5} = Rn;
3098 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3101 def : InstAlias<asm # " $Rt, $Rt2, [$Rn]",
3103 GPR64sp:$Rn, 0)>;
3112 GPR64sp:$Rn, indextype:$offset),
3116 def : InstAlias<asm # " $Rt, $Rt2, [$Rn]",
3118 GPR64sp:$Rn, 0)>;
3124 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]!", "$Rn = $wback,@earlyclobber $wback", []> {
3127 bits<5> Rn;
3136 let Inst{9-5} = Rn;
3148 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3156 GPR64sp:$Rn, indextype:$offset),
3165 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn], $offset", "$Rn = $wback,@earlyclobber $wback", []> {
3168 bits<5> Rn;
3177 let Inst{9-5} = Rn;
3189 (ins GPR64sp:$Rn, idxtype:$offset), asm>,
3197 GPR64sp:$Rn, idxtype:$offset),
3206 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
3209 bits<5> Rn;
3218 let Inst{9-5} = Rn;
3229 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3233 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3235 GPR64sp:$Rn, 0)>;
3243 GPR64sp:$Rn, indextype:$offset),
3247 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3249 GPR64sp:$Rn, 0)>;
3269 // the other register fields since Rt and Rn are always used.
3290 bits<5> Rn;
3295 let Inst{9-5} = Rn;
3306 (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]">,
3312 (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]">,
3319 (ins GPR64sp0:$Rn), asm,
3320 "\t$Rt, $Rt2, [$Rn]">,
3324 bits<5> Rn;
3326 let Inst{9-5} = Rn;
3337 (ins regtype:$Rt, GPR64sp0:$Rn),
3338 asm, "\t$Rt, [$Rn]">,
3345 (ins regtype:$Rt, GPR64sp0:$Rn),
3346 asm, "\t$Ws, $Rt, [$Rn]">,
3350 bits<5> Rn;
3352 let Inst{9-5} = Rn;
3363 (ins regtype:$Rt, regtype:$Rt2, GPR64sp0:$Rn),
3364 asm, "\t$Ws, $Rt, $Rt2, [$Rn]">,
3369 bits<5> Rn;
3372 let Inst{9-5} = Rn;
3403 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3404 asm, "\t$Rd, $Rn", "", pattern>,
3407 bits<5> Rn;
3415 let Inst{9-5} = Rn;
3423 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3424 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3427 bits<5> Rn;
3436 let Inst{9-5} = Rn;
3444 [(set GPR32:$Rd, (OpN FPR32:$Rn))]> {
3450 [(set GPR64:$Rd, (OpN FPR32:$Rn))]> {
3456 [(set GPR32:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3462 [(set GPR64:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3472 [(set GPR32:$Rd, (OpN (fmul FPR32:$Rn,
3481 [(set GPR64:$Rd, (OpN (fmul FPR32:$Rn,
3489 [(set GPR32:$Rd, (OpN (fmul FPR64:$Rn,
3498 [(set GPR64:$Rd, (OpN (fmul FPR64:$Rn,
3512 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3513 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3516 bits<5> Rn;
3522 let Inst{9-5} = Rn;
3529 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3530 asm, "\t$Rd, $Rn", "", [(set (dvt dstType:$Rd), (node srcType:$Rn))]>,
3533 bits<5> Rn;
3539 let Inst{9-5} = Rn;
3568 (fdiv (node GPR32:$Rn),
3577 (fdiv (node GPR32:$Rn),
3586 (fdiv (node GPR64:$Rn),
3594 (fdiv (node GPR64:$Rn),
3609 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "",
3615 [/*(set (dvt dstType:$Rd), (bitconvert (svt srcType:$Rn)))*/]>,
3618 bits<5> Rn;
3624 let Inst{9-5} = Rn;
3632 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
3633 "{\t$Rd"#kind#"$idx, $Rn|"#kind#"\t$Rd$idx, $Rn}", "", []>,
3636 bits<5> Rn;
3642 let Inst{9-5} = Rn;
3652 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
3653 "{\t$Rd, $Rn"#kind#"$idx|"#kind#"\t$Rd, $Rn$idx}", "", []>,
3656 bits<5> Rn;
3662 let Inst{9-5} = Rn;
3710 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", pattern>,
3713 bits<5> Rn;
3719 let Inst{9-5} = Rn;
3726 [(set FPR16:$Rd, (fround FPR64:$Rn))]>;
3730 [(set FPR32:$Rd, (fround FPR64:$Rn))]>;
3734 [(set FPR64:$Rd, (fextend FPR16:$Rn))]>;
3738 [(set FPR32:$Rd, (fextend FPR16:$Rn))]>;
3742 [(set FPR64:$Rd, (fextend FPR32:$Rn))]>;
3746 [(set FPR16:$Rd, (fround FPR32:$Rn))]>;
3756 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
3757 [(set (vt regtype:$Rd), (node (vt regtype:$Rn)))]>,
3760 bits<5> Rn;
3765 let Inst{9-5} = Rn;
3787 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
3788 asm, "\t$Rd, $Rn, $Rm", "", pat>,
3791 bits<5> Rn;
3798 let Inst{9-5} = Rn;
3806 (node (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]> {
3812 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]> {
3819 [(set FPR32:$Rd, (fneg (node FPR32:$Rn, (f32 FPR32:$Rm))))]> {
3824 [(set FPR64:$Rd, (fneg (node FPR64:$Rn, (f64 FPR64:$Rm))))]> {
3836 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, regtype: $Ra),
3837 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pat>,
3840 bits<5> Rn;
3848 let Inst{9-5} = Rn;
3856 (node (f32 FPR32:$Rn), (f32 FPR32:$Rm), (f32 FPR32:$Ra)))]> {
3862 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm), (f64 FPR64:$Ra)))]> {
3875 : I<(outs), (ins regtype:$Rn), asm, "\t$Rn, #0.0", "", pat>,
3877 bits<5> Rn;
3882 let Inst{9-5} = Rn;
3893 : I<(outs), (ins regtype:$Rn, regtype:$Rm), asm, "\t$Rn, $Rm", "", pat>,
3896 bits<5> Rn;
3901 let Inst{9-5} = Rn;
3910 [(OpNode FPR32:$Rn, (f32 FPR32:$Rm)), (implicit NZCV)]> {
3915 [(OpNode (f32 FPR32:$Rn), fpimm0), (implicit NZCV)]> {
3920 [(OpNode FPR64:$Rn, (f64 FPR64:$Rm)), (implicit NZCV)]> {
3925 [(OpNode (f64 FPR64:$Rn), fpimm0), (implicit NZCV)]> {
3938 : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
3939 asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
3941 bits<5> Rn;
3951 let Inst{9-5} = Rn;
3973 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
3974 asm, "\t$Rd, $Rn, $Rm, $cond", "",
3976 (AArch64csel (vt regtype:$Rn), regtype:$Rm,
3980 bits<5> Rn;
3989 let Inst{9-5} = Rn;
4047 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
4048 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
4049 "|" # kind # "\t$Rd, $Rn, $Rm|}", "", pattern>,
4052 bits<5> Rn;
4063 let Inst{9-5} = Rn;
4071 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn, regtype:$Rm), asm,
4072 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
4073 "|" # kind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
4076 bits<5> Rn;
4087 let Inst{9-5} = Rn;
4096 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4099 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4102 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4105 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4108 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4111 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4114 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
4122 [(set V64:$Rd, (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))]>;
4125 [(set V128:$Rd, (v16i8 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm))))]>;
4128 [(set V64:$Rd, (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))]>;
4131 [(set V128:$Rd, (v8i16 (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm))))]>;
4134 [(set V64:$Rd, (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))]>;
4137 [(set V128:$Rd, (v4i32 (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
4145 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4149 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4153 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4157 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4161 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4165 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4173 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4177 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4185 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4188 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4191 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4199 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4202 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4205 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4213 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4217 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4221 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4229 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4232 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4235 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4238 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4246 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn, V64:$Rm))]>;
4249 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn, V128:$Rm))]>;
4271 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4275 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
4314 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4315 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4316 "|" # dstkind # "\t$Rd, $Rn}", "", pattern>,
4319 bits<5> Rn;
4328 let Inst{9-5} = Rn;
4336 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn), asm,
4337 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4338 "|" # dstkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4341 bits<5> Rn;
4350 let Inst{9-5} = Rn;
4359 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4362 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4365 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4368 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4371 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4374 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4380 : I<(outs V128:$Rd), (ins regtype:$Rn), asm,
4381 "{\t$Rd" # dstkind # ", $Rn" # srckind # ", #" # amount #
4382 "|" # dstkind # "\t$Rd, $Rn, #" # amount # "}", "", []>,
4385 bits<5> Rn;
4391 let Inst{9-5} = Rn;
4417 [(set (v4i16 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4420 [(set (v8i16 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4423 [(set (v2i32 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4426 [(set (v4i32 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4429 [(set (v1i64 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4432 [(set (v2i64 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4440 (v8i8 V64:$Rn)))]>;
4444 (v16i8 V128:$Rn)))]>;
4448 (v4i16 V64:$Rn)))]>;
4452 (v8i16 V128:$Rn)))]>;
4456 (v2i32 V64:$Rn)))]>;
4460 (v4i32 V128:$Rn)))]>;
4468 [(set (v8i8 V64:$dst), (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn)))]>;
4471 [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
4474 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn)))]>;
4477 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn)))]>;
4480 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn)))]>;
4483 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
4486 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn)))]>;
4493 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4496 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4499 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4502 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4505 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4508 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4511 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4520 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4523 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4532 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn))]>;
4535 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn))]>;
4538 [(set (v4i16 V64:$Rd), (OpNode V64:$Rn))]>;
4541 [(set (v8i16 V128:$Rd), (OpNode V128:$Rn))]>;
4550 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4553 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4556 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4564 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4567 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4575 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4578 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4581 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4588 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4591 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4594 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4602 : I<(outs outreg:$Rd), (ins inreg:$Rn), asm,
4603 "{\t$Rd" # outkind # ", $Rn" # inkind #
4604 "|" # outkind # "\t$Rd, $Rn}", "", pattern>,
4607 bits<5> Rn;
4616 let Inst{9-5} = Rn;
4624 : I<(outs outreg:$dst), (ins outreg:$Rd, inreg:$Rn), asm,
4625 "{\t$Rd" # outkind # ", $Rn" # inkind #
4626 "|" # outkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4629 bits<5> Rn;
4638 let Inst{9-5} = Rn;
4646 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4651 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4656 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4660 def : Pat<(concat_vectors (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn))),
4662 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4663 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn))),
4665 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4666 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn))),
4668 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4675 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4676 "{\t$Rd" # kind # ", $Rn" # kind # ", #" # zero #
4677 "|" # kind # "\t$Rd, $Rn, #" # zero # "}", "",
4678 [(set (dty regtype:$Rd), (OpNode (sty regtype:$Rn)))]>,
4681 bits<5> Rn;
4690 let Inst{9-5} = Rn;
4753 : I<(outs outtype:$Rd), (ins intype:$Rn), asm,
4754 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "", pattern>,
4757 bits<5> Rn;
4766 let Inst{9-5} = Rn;
4774 : I<(outs outtype:$dst), (ins outtype:$Rd, intype:$Rn), asm,
4775 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "$Rd = $dst", pattern>,
4778 bits<5> Rn;
4787 let Inst{9-5} = Rn;
4817 [(set (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4821 def : Pat<(concat_vectors (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn))),
4823 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4836 : I<(outs outtype:$Rd), (ins intype1:$Rn, intype2:$Rm), asm,
4837 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
4838 "|" # outkind # "\t$Rd, $Rn, $Rm}", "", pattern>,
4841 bits<5> Rn;
4852 let Inst{9-5} = Rn;
4862 : I<(outs outtype:$dst), (ins outtype:$Rd, intype1:$Rn, intype2:$Rm), asm,
4863 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
4864 "|" # outkind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
4867 bits<5> Rn;
4878 let Inst{9-5} = Rn;
4891 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4899 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4907 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
4916 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
4920 V128:$Rn, V128:$Rm)>;
4921 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
4925 V128:$Rn, V128:$Rm)>;
4926 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
4930 V128:$Rn, V128:$Rm)>;
4938 [(set (v8i16 V128:$Rd), (IntOp (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4951 def : Pat<(v8i16 (IntOp (v8i8 (extract_high_v16i8 V128:$Rn)),
4953 (!cast<Instruction>(NAME#"v16i8") V128:$Rn, V128:$Rm)>;
4961 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4965 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
4970 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4974 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
4984 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))))]>;
4989 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
4995 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))))]>;
5000 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
5006 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))))]>;
5011 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
5023 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))))]>;
5029 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
5036 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))))]>;
5042 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
5049 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))))]>;
5055 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
5064 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5068 [(set (v8i16 V128:$Rd), (OpNode (extract_high_v16i8 V128:$Rn),
5073 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5077 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
5082 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5086 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
5097 (OpNode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5103 (extract_high_v16i8 V128:$Rn),
5109 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5115 (extract_high_v8i16 V128:$Rn),
5121 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5127 (extract_high_v4i32 V128:$Rn),
5138 (v4i32 (int_aarch64_neon_sqdmull (v4i16 V64:$Rn),
5145 (v4i32 (int_aarch64_neon_sqdmull (extract_high_v8i16 V128:$Rn),
5152 (v2i64 (int_aarch64_neon_sqdmull (v2i32 V64:$Rn),
5159 (v2i64 (int_aarch64_neon_sqdmull (extract_high_v4i32 V128:$Rn),
5168 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i8 V64:$Rm)))]>;
5172 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
5177 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i16 V64:$Rm)))]>;
5181 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
5186 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i32 V64:$Rm)))]>;
5190 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
5200 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, i32imm:$imm), asm,
5201 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $imm" #
5202 "|" # kind # "\t$Rd, $Rn, $Rm, $imm}", "",
5204 (AArch64ext regtype:$Rn, regtype:$Rm, (i32 imm:$imm)))]>,
5207 bits<5> Rn;
5217 let Inst{9-5} = Rn;
5235 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5236 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
5237 "|" # kind # "\t$Rd, $Rn, $Rm}", "",
5238 [(set (valty regtype:$Rd), (OpNode regtype:$Rn, regtype:$Rm))]>,
5241 bits<5> Rn;
5252 let Inst{9-5} = Rn;
5273 def : Pat<(v4f16 (OpNode V64:$Rn, V64:$Rm)),
5274 (!cast<Instruction>(NAME#"v4i16") V64:$Rn, V64:$Rm)>;
5275 def : Pat<(v8f16 (OpNode V128:$Rn, V128:$Rm)),
5276 (!cast<Instruction>(NAME#"v8i16") V128:$Rn, V128:$Rm)>;
5277 def : Pat<(v2f32 (OpNode V64:$Rn, V64:$Rm)),
5278 (!cast<Instruction>(NAME#"v2i32") V64:$Rn, V64:$Rm)>;
5279 def : Pat<(v4f32 (OpNode V128:$Rn, V128:$Rm)),
5280 (!cast<Instruction>(NAME#"v4i32") V128:$Rn, V128:$Rm)>;
5281 def : Pat<(v2f64 (OpNode V128:$Rn, V128:$Rm)),
5282 (!cast<Instruction>(NAME#"v2i64") V128:$Rn, V128:$Rm)>;
5293 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5294 "\t$Rd, $Rn, $Rm", "", pattern>,
5297 bits<5> Rn;
5307 let Inst{9-5} = Rn;
5315 : I<oops, iops, asm, "\t$Rd, $Rn, $Rm", "$Rd = $dst", pattern>,
5318 bits<5> Rn;
5328 let Inst{9-5} = Rn;
5335 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5341 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5346 def : Pat<(i64 (OpNode (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5347 (!cast<Instruction>(NAME#"v1i64") FPR64:$Rn, FPR64:$Rm)>;
5348 def : Pat<(i32 (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm))),
5349 (!cast<Instruction>(NAME#"v1i32") FPR32:$Rn, FPR32:$Rm)>;
5355 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5362 (ins FPR32:$Rd, FPR32:$Rn, FPR32:$Rm),
5365 (ins FPR16:$Rd, FPR16:$Rn, FPR16:$Rm),
5373 [(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5375 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5378 def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5379 (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
5386 [(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5388 [(set (i32 FPR32:$Rd), (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]>;
5391 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5392 (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
5398 "\t$Rd, $Rn, $Rm", cstr, pat>,
5401 bits<5> Rn;
5411 let Inst{9-5} = Rn;
5420 (ins FPR16:$Rn, FPR16:$Rm), asm, "", []>;
5423 (ins FPR32:$Rn, FPR32:$Rm), asm, "",
5424 [(set (i64 FPR64:$Rd), (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5432 (ins FPR32:$Rd, FPR16:$Rn, FPR16:$Rm),
5436 (ins FPR64:$Rd, FPR32:$Rn, FPR32:$Rm),
5439 (OpNode (i64 FPR64:$Rd), (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5450 : I<(outs regtype:$Rd), (ins regtype2:$Rn), asm,
5451 "\t$Rd, $Rn", "", pat>,
5454 bits<5> Rn;
5462 let Inst{9-5} = Rn;
5470 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype2:$Rn), asm,
5471 "\t$Rd, $Rn", "$Rd = $dst", pat>,
5474 bits<5> Rn;
5482 let Inst{9-5} = Rn;
5490 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
5491 "\t$Rd, $Rn, #" # zero, "", []>,
5494 bits<5> Rn;
5502 let Inst{9-5} = Rn;
5507 : I<(outs FPR32:$Rd), (ins FPR64:$Rn), asm, "\t$Rd, $Rn", "",
5508 [(set (f32 FPR32:$Rd), (int_aarch64_sisd_fcvtxn (f64 FPR64:$Rn)))]>,
5511 bits<5> Rn;
5515 let Inst{9-5} = Rn;
5523 def : Pat<(v1i64 (OpNode FPR64:$Rn)),
5524 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
5532 def : InstAlias<asm # " $Rd, $Rn, #0",
5533 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rd, FPR64:$Rn), 0>;
5534 def : InstAlias<asm # " $Rd, $Rn, #0",
5535 (!cast<Instruction>(NAME # v1i32rz) FPR32:$Rd, FPR32:$Rn), 0>;
5537 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))),
5538 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
5544 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
5546 def : Pat<(i64 (OpNode (i64 FPR64:$Rn))),
5547 (!cast<Instruction>(NAME # "v1i64") FPR64:$Rn)>;
5558 [(set FPR64:$Rd, (OpNode (f64 FPR64:$Rn)))]>;
5560 [(set FPR32:$Rd, (OpNode (f32 FPR32:$Rn)))]>;
5567 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5569 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
5574 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn))),
5575 (!cast<Instruction>(NAME # v1i64) FPR64:$Rn)>;
5582 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn)))]>;
5584 [(set (i32 FPR32:$dst), (OpNode (i32 FPR32:$Rd), (i32 FPR32:$Rn)))]>;
5589 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn))),
5590 (!cast<Instruction>(NAME # v1i64) FPR64:$Rd, FPR64:$Rn)>;
5599 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5612 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5613 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", []>,
5616 bits<5> Rn;
5624 let Inst{9-5} = Rn;
5648 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5649 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", pattern>,
5652 bits<5> Rn;
5661 let Inst{9-5} = Rn;
5696 [(set FPR32:$Rd, (intOp (v4f32 V128:$Rn)))]>;
5710 bits<5> Rn;
5717 let Inst{9-5} = Rn;
5723 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins regtype:$Rn), "dup",
5724 "{\t$Rd" # size # ", $Rn" #
5725 "|" # size # "\t$Rd, $Rn}", "",
5726 [(set (vectype vecreg:$Rd), (AArch64dup regtype:$Rn))]> {
5735 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins V128:$Rn, idxtype:$idx), "dup",
5736 "{\t$Rd" # dstkind # ", $Rn" # srckind # "$idx" #
5737 "|" # dstkind # "\t$Rd, $Rn$idx}", "",
5739 (OpNode (insreg V128:$Rn), idxtype:$idx))]> {
5780 : BaseSIMDInsDup<Q, 0, (outs regtype:$Rd), (ins V128:$Rn, idxtype:$idx), asm,
5781 "{\t$Rd, $Rn" # size # "$idx" #
5782 "|" # size # "\t$Rd, $Rn$idx}", "", pattern> {
5792 [(set regtype:$Rd, (vector_extract (vectype V128:$Rn), idxtype:$idx))]>;
5860 (ins V128:$Rd, idxtype:$idx, regtype:$Rn), "ins",
5861 "{\t$Rd" # size # "$idx, $Rn" #
5862 "|" # size # "\t$Rd$idx, $Rn}",
5865 (vector_insert (vectype V128:$Rd), regtype:$Rn, idxtype:$idx))]> {
5872 (ins V128:$Rd, idxtype:$idx, V128:$Rn, idxtype:$idx2), "ins",
5873 "{\t$Rd" # size # "$idx, $Rn" # size # "$idx2" #
5874 "|" # size # "\t$Rd$idx, $Rn$idx2}",
5879 (elttype (vector_extract (vectype V128:$Rn), idxtype:$idx2)),
6349 : I<(outs dst_reg:$Rd), (ins lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx),
6351 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6352 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "", pattern>,
6355 bits<5> Rn;
6369 let Inst{9-5} = Rn;
6380 (ins dst_reg:$Rd, lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx), asm,
6381 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6382 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "$Rd = $dst", pattern>,
6385 bits<5> Rn;
6399 let Inst{9-5} = Rn;
6410 (OpNode (v2f32 V64:$Rn),
6422 (OpNode (v4f32 V128:$Rn),
6434 (OpNode (v2f64 V128:$Rn),
6445 (OpNode (f32 FPR32Op:$Rn),
6457 (OpNode (f64 FPR64Op:$Rn),
6468 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6472 V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6473 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6475 (!cast<Instruction>(INST # "v2i32_indexed") V64:$Rd, V64:$Rn,
6480 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6484 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6485 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6487 (!cast<Instruction>(INST # "v4i32_indexed") V128:$Rd, V128:$Rn,
6491 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6495 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6496 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6498 (!cast<Instruction>(INST # "v2i64_indexed") V128:$Rd, V128:$Rn,
6502 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6504 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6506 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6508 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6512 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
6514 (!cast<Instruction>(INST # "v1i64_indexed") FPR64:$Rd, FPR64:$Rn,
6569 (OpNode (v4i16 V64:$Rn),
6582 (OpNode (v8i16 V128:$Rn),
6595 (OpNode (v2i32 V64:$Rn),
6607 (OpNode (v4i32 V128:$Rn),
6627 (OpNode FPR32Op:$Rn,
6643 (OpNode (v4i16 V64:$Rn),
6656 (OpNode (v8i16 V128:$Rn),
6669 (OpNode (v2i32 V64:$Rn),
6681 (OpNode (v4i32 V128:$Rn),
6695 (OpNode (v4i16 V64:$Rd),(v4i16 V64:$Rn),
6708 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
6721 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
6733 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
6748 (OpNode (v4i16 V64:$Rn),
6761 (OpNode (extract_high_v8i16 V128:$Rn),
6776 (OpNode (v2i32 V64:$Rn),
6788 (OpNode (extract_high_v4i32 V128:$Rn),
6823 (v4i16 V64:$Rn),
6836 (int_aarch64_neon_sqdmull (v4i16 V64:$Rn),
6842 (SUBREG_TO_REG (i32 0), FPR32Op:$Rd, ssub), V64:$Rn,
6853 (extract_high_v8i16 V128:$Rn),
6870 (v2i32 V64:$Rn),
6885 (extract_high_v4i32 V128:$Rn),
6910 (i32 FPR32Op:$Rn),
6928 (OpNode (v4i16 V64:$Rn),
6941 (OpNode (extract_high_v8i16 V128:$Rn),
6956 (OpNode (v2i32 V64:$Rn),
6968 (OpNode (extract_high_v4i32 V128:$Rn),
6986 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn),
7000 (extract_high_v8i16 V128:$Rn),
7014 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn),
7027 (extract_high_v4i32 V128:$Rn),
7045 : I<(outs regtype1:$Rd), (ins regtype2:$Rn, immtype:$imm),
7046 asm, "\t$Rd, $Rn, $imm", "", pattern>,
7049 bits<5> Rn;
7057 let Inst{9-5} = Rn;
7065 : I<(outs regtype1:$dst), (ins regtype1:$Rd, regtype2:$Rn, immtype:$imm),
7066 asm, "\t$Rd, $Rn, $imm", "$Rd = $dst", pattern>,
7069 bits<5> Rn;
7077 let Inst{9-5} = Rn;
7099 (OpNode (i64 FPR64:$Rn), (i32 vecshiftR64:$imm)))]> {
7103 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftR64:$imm))),
7104 (!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftR64:$imm)>;
7111 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn),
7116 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
7118 (!cast<Instruction>(NAME # "d") FPR64:$Rd, FPR64:$Rn,
7127 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
7155 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn), vecshiftR32:$imm))]> {
7174 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn), (i32 vecshiftL32:$imm)))]> {
7180 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
7184 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm))),
7185 (!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftL64:$imm)>;
7220 : I<(outs dst_reg:$Rd), (ins src_reg:$Rn, immtype:$imm),
7221 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7222 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "", pattern>,
7225 bits<5> Rn;
7233 let Inst{9-5} = Rn;
7243 : I<(outs vectype1:$dst), (ins vectype1:$Rd, vectype2:$Rn, immtype:$imm),
7244 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7245 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "$Rd = $dst", pattern>,
7248 bits<5> Rn;
7256 let Inst{9-5} = Rn;
7265 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (i32 imm:$imm)))]> {
7273 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (i32 imm:$imm)))]> {
7281 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (i32 imm:$imm)))]> {
7292 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (i32 imm:$imm)))]> {
7300 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (i32 imm:$imm)))]> {
7308 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (i32 imm:$imm)))]> {
7319 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))]> {
7335 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))]> {
7351 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))]> {
7369 def : Pat<(concat_vectors (v8i8 V64:$Rd),(OpNode (v8i16 V128:$Rn),
7373 V128:$Rn, vecshiftR16Narrow:$imm)>;
7374 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn),
7378 V128:$Rn, vecshiftR32Narrow:$imm)>;
7379 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn),
7383 V128:$Rn, vecshiftR64Narrow:$imm)>;
7391 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7400 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7409 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7418 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7427 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7436 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7445 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7457 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7466 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7475 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7484 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7493 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7502 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7511 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7524 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
7533 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
7542 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
7551 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7560 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7569 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7578 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
7591 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
7601 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
7611 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
7621 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7631 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7641 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7651 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
7662 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), vecshiftL8:$imm))]> {
7671 (OpNode (extract_high_v16i8 V128:$Rn), vecshiftL8:$imm))]> {
7678 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), vecshiftL16:$imm))]> {
7687 (OpNode (extract_high_v8i16 V128:$Rn), vecshiftL16:$imm))]> {
7695 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), vecshiftL32:$imm))]> {
7704 (OpNode (extract_high_v4i32 V128:$Rn), vecshiftL32:$imm))]> {
7721 : I<oops, iops, asm, "\t$Vt, [$Rn]", "", pattern> {
7723 bits<5> Rn;
7731 let Inst{9-5} = Rn;
7737 : I<oops, iops, asm, "\t$Vt, [$Rn], $Xm", "$Rn = $wback", []> {
7739 bits<5> Rn;
7749 let Inst{9-5} = Rn;
7758 // "ld1\t$Vt, [$Rn], #16"
7760 // (LD1Twov8b_POST VecListTwo8b:$Vt, GPR64sp:$Rn, XZR)
7761 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
7763 GPR64sp:$Rn,
7768 // "ld1.8b\t$Vt, [$Rn], #16"
7770 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, XZR)
7771 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], #" # Offset,
7773 GPR64sp:$Rn,
7778 // "ld1\t$Vt, [$Rn]"
7780 // (LD1Twov8b VecListTwo64:$Vt, GPR64sp:$Rn)
7781 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn]",
7784 GPR64sp:$Rn), 0>;
7787 // "ld1\t$Vt, [$Rn], $Xm"
7789 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, GPR64pi8:$Xm)
7790 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
7792 GPR64sp:$Rn,
7802 (ins GPR64sp:$Rn), []>;
7805 (ins GPR64sp:$Rn), []>;
7808 (ins GPR64sp:$Rn), []>;
7811 (ins GPR64sp:$Rn), []>;
7814 (ins GPR64sp:$Rn), []>;
7817 (ins GPR64sp:$Rn), []>;
7820 (ins GPR64sp:$Rn), []>;
7826 (ins GPR64sp:$Rn,
7831 (ins GPR64sp:$Rn,
7836 (ins GPR64sp:$Rn,
7841 (ins GPR64sp:$Rn,
7846 (ins GPR64sp:$Rn,
7851 (ins GPR64sp:$Rn,
7856 (ins GPR64sp:$Rn,
7875 GPR64sp:$Rn), []>;
7878 GPR64sp:$Rn), []>;
7881 GPR64sp:$Rn), []>;
7884 GPR64sp:$Rn), []>;
7887 GPR64sp:$Rn), []>;
7890 GPR64sp:$Rn), []>;
7893 GPR64sp:$Rn), []>;
7898 GPR64sp:$Rn,
7903 GPR64sp:$Rn,
7908 GPR64sp:$Rn,
7913 GPR64sp:$Rn,
7918 GPR64sp:$Rn,
7923 GPR64sp:$Rn,
7928 GPR64sp:$Rn,
7949 (ins GPR64sp:$Rn), []>;
7954 (ins GPR64sp:$Rn,
7969 GPR64sp:$Rn), []>;
7974 GPR64sp:$Rn,
8028 bits<5> Rn;
8034 let Inst{9-5} = Rn;
8043 bits<5> Rn;
8049 let Inst{9-5} = Rn;
8057 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn]", "",
8058 (outs listtype:$Vt), (ins GPR64sp:$Rn),
8069 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn], $Xm",
8070 "$Rn = $wback",
8072 (ins GPR64sp:$Rn, GPR64pi:$Xm), []> {
8084 // "ld1r.8b\t$Vt, [$Rn], #1"
8086 // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR)
8087 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
8089 GPR64sp:$Rn,
8094 // "ld1r.8b\t$Vt, [$Rn], #1"
8096 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR)
8097 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], #" # Offset,
8099 GPR64sp:$Rn,
8104 // "ld1r.8b\t$Vt, [$Rn]"
8106 // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn)
8107 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn]",
8110 GPR64sp:$Rn), 0>;
8113 // "ld1r.8b\t$Vt, [$Rn], $Xm"
8115 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
8116 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
8118 GPR64sp:$Rn,
8179 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8191 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8203 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8204 "$Rn = $wback", oops, iops, []> {
8216 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8217 "$Rn = $wback", oops, iops, []> {
8230 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8243 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8257 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8258 "$Rn = $wback", oops, iops, []> {
8271 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8272 "$Rn = $wback", oops, iops, []> {
8285 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8297 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8309 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8310 "$Rn = $wback", oops, iops, []> {
8322 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8323 "$Rn = $wback", oops, iops, []> {
8335 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8347 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8359 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8360 "$Rn = $wback", oops, iops, []> {
8372 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8373 "$Rn = $wback", oops, iops, []> {
8391 GPR64sp:$Rn), []>;
8396 GPR64sp:$Rn, GPR64pi:$Xm)>;
8405 GPR64sp:$Rn), []>;
8410 GPR64sp:$Rn, GPR64pi:$Xm)>;
8419 GPR64sp:$Rn), []>;
8424 GPR64sp:$Rn, GPR64pi:$Xm)>;
8432 GPR64sp:$Rn), []>;
8437 GPR64sp:$Rn, GPR64pi:$Xm)>;
8444 GPR64sp:$Rn), []>;
8449 GPR64sp:$Rn, GPR64pi:$Xm)>;
8456 GPR64sp:$Rn), []>;
8461 GPR64sp:$Rn, GPR64pi:$Xm)>;
8468 GPR64sp:$Rn), []>;
8473 GPR64sp:$Rn, GPR64pi:$Xm)>;
8480 GPR64sp:$Rn), []>;
8485 GPR64sp:$Rn, GPR64pi:$Xm)>;
8491 // "ld1\t$Vt, [$Rn], #1"
8493 // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR)
8494 def : InstAlias<asm # "\t$Vt$idx, [$Rn], #" # Offset,
8496 GPR64sp:$Rn,
8501 // "ld1.8b\t$Vt, [$Rn], #1"
8503 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR)
8504 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], #" # Offset,
8506 GPR64sp:$Rn,
8511 // "ld1.8b\t$Vt, [$Rn]"
8513 // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn)
8514 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn]",
8517 idxtype:$idx, GPR64sp:$Rn), 0>;
8520 // "ld1.8b\t$Vt, [$Rn], $Xm"
8522 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
8523 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], $Xm",
8525 GPR64sp:$Rn,
8578 (v4i16 (int_aarch64_neon_sqrdmulh (v4i16 V64:$Rn),
8583 (v8i16 (int_aarch64_neon_sqrdmulh (v8i16 V128:$Rn),
8588 (v2i32 (int_aarch64_neon_sqrdmulh (v2i32 V64:$Rn),
8593 (v4i32 (int_aarch64_neon_sqrdmulh (v4i32 V128:$Rn),
8605 (v4i16 V64:$Rn),
8620 (v8i16 V128:$Rn),
8635 (v2i32 V64:$Rn),
8652 (v2i32 V64:$Rn),
8663 V64:$Rn,
8674 (v4i32 V128:$Rn),
8687 (v4i32 V128:$Rn),
8697 V128:$Rn,
8718 (i32 FPR32Op:$Rn),
8736 : I<outs, ins, asm, "{\t$Rd.16b, $Rn.16b|.16b\t$Rd, $Rn}", cstr, pat>,
8739 bits<5> Rn;
8743 let Inst{9-5} = Rn;
8748 : AESBase<opc, asm, (outs V128:$Rd), (ins V128:$Rn), "",
8749 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
8752 : AESBase<opc, asm, (outs V128:$dst), (ins V128:$Rd, V128:$Rn),
8755 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
8761 "{\t$Rd" # dst_lhs_kind # ", $Rn" # dst_lhs_kind # ", $Rm.4s" #
8762 "|.4s\t$Rd, $Rn, $Rm}", "$Rd = $dst", pat>,
8765 bits<5> Rn;
8772 let Inst{9-5} = Rn;
8778 (ins FPR128:$Rd, FPR32:$Rn, V128:$Rm),
8780 (OpNode (v4i32 FPR128:$Rd), (i32 FPR32:$Rn),
8785 (ins V128:$Rd, V128:$Rn, V128:$Rm),
8787 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
8792 (ins FPR128:$Rd, FPR128:$Rn, V128:$Rm),
8794 (OpNode (v4i32 FPR128:$Rd), (v4i32 FPR128:$Rn),
8801 : I<oops, iops, asm, "{\t$Rd" # kind # ", $Rn" # kind #
8802 "|" # kind # "\t$Rd, $Rn}", cstr, pat>,
8805 bits<5> Rn;
8809 let Inst{9-5} = Rn;
8815 (ins V128:$Rd, V128:$Rn),
8817 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
8820 : SHA2OpInst<opc, asm, "", "", (outs FPR32:$Rd), (ins FPR32:$Rn),
8821 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;