Lines Matching refs:NZCV
321 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
348 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
812 if (Instr.modifiesRegister(AArch64::NZCV, TRI) || in modifiesConditionCode()
813 (!CheckOnlyCCWrites && Instr.readsRegister(AArch64::NZCV, TRI))) in modifiesConditionCode()
831 int Cmp_NZCV = CmpInstr->findRegisterDefOperandIdx(AArch64::NZCV, true); in optimizeCompareInstr()
915 if (MO.isRegMask() && MO.clobbersPhysReg(AArch64::NZCV)) { in optimizeCompareInstr()
919 if (!MO.isReg() || MO.getReg() != AArch64::NZCV) in optimizeCompareInstr()
970 if (MBB->isLiveIn(AArch64::NZCV)) in optimizeCompareInstr()
980 MI->addRegisterDefined(AArch64::NZCV, TRI); in optimizeCompareInstr()
1797 if (DestReg == AArch64::NZCV) { in copyPhysReg()
1800 .addImm(AArch64SysReg::NZCV) in copyPhysReg()
1802 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define); in copyPhysReg()
1806 if (SrcReg == AArch64::NZCV) { in copyPhysReg()
1810 .addImm(AArch64SysReg::NZCV) in copyPhysReg()
1811 .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
2481 int Cmp_NZCV = Root.findRegisterDefOperandIdx(AArch64::NZCV, true); in hasPattern()
2940 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) != -1) in optimizeCondBranch()