Lines Matching refs:ZeroReg
2440 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL() argument
2455 if (MI->getOperand(3).getReg() != ZeroReg) in canCombineWithMUL()
2731 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
2736 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
2743 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
2759 .addReg(ZeroReg) in genAlternativeCodeSequence()
2775 unsigned SubOpc, ZeroReg; in genAlternativeCodeSequence() local
2779 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
2785 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
2793 .addReg(ZeroReg) in genAlternativeCodeSequence()
2823 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
2828 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
2835 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
2850 .addReg(ZeroReg) in genAlternativeCodeSequence()