71                            DebugLoc DL,
77                                  DebugLoc DL,
83                         DebugLoc DL,
88                                DebugLoc DL,
93                                 DebugLoc DL, unsigned DReg, unsigned Lane,
98                                DebugLoc DL);
432                               DebugLoc DL,  in createDupLane()  argument
438                          DL,  in createDupLane()
451                                     DebugLoc DL,  in createExtractSubreg()  argument
457           DL,  in createExtractSubreg()
468                                   DebugLoc DL,  in createRegSequence()  argument
473           DL,  in createRegSequence()
487                            DebugLoc DL,  in createVExt()  argument
492                          DL,  in createVExt()
503                                    DebugLoc DL, unsigned DReg, unsigned Lane,  in createInsertSubreg()  argument
508           DL,  in createInsertSubreg()
520                                   DebugLoc DL) {  in createImplicitDef()  argument
524           DL,  in createImplicitDef()
535   DebugLoc DL = MI->getDebugLoc();  in optimizeAllLanesPattern()  local
544     unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,  in optimizeAllLanesPattern()
546     unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,  in optimizeAllLanesPattern()
549     unsigned Out1 = createDupLane(MBB, InsertPt, DL, DSub0, 0);  in optimizeAllLanesPattern()
550     unsigned Out2 = createDupLane(MBB, InsertPt, DL, DSub0, 1);  in optimizeAllLanesPattern()
551     Out = createVExt(MBB, InsertPt, DL, Out1, Out2);  in optimizeAllLanesPattern()
553     unsigned Out3 = createDupLane(MBB, InsertPt, DL, DSub1, 0);  in optimizeAllLanesPattern()
554     unsigned Out4 = createDupLane(MBB, InsertPt, DL, DSub1, 1);  in optimizeAllLanesPattern()
555     Out2 = createVExt(MBB, InsertPt, DL, Out3, Out4);  in optimizeAllLanesPattern()
557     Out = createRegSequence(MBB, InsertPt, DL, Out, Out2);  in optimizeAllLanesPattern()
560     unsigned Out1 = createDupLane(MBB, InsertPt, DL, Reg, 0);  in optimizeAllLanesPattern()
561     unsigned Out2 = createDupLane(MBB, InsertPt, DL, Reg, 1);  in optimizeAllLanesPattern()
562     Out = createVExt(MBB, InsertPt, DL, Out1, Out2);  in optimizeAllLanesPattern()
580     Out = createImplicitDef(MBB, InsertPt, DL);  in optimizeAllLanesPattern()
581     Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);  in optimizeAllLanesPattern()
582     Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);  in optimizeAllLanesPattern()