Lines Matching refs:addReg

135         .addReg(ThumbIndirectPads[i].first)  in runOnMachineFunction()
138 .addReg(0)); in runOnMachineFunction()
1015 .addReg(0)); in EmitJump2Table()
1221 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
1225 .addReg(MI->getOperand(3).getReg())); in EmitInstruction()
1238 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
1242 .addReg(MI->getOperand(4).getReg())); in EmitInstruction()
1249 .addReg(ARM::LR) in EmitInstruction()
1250 .addReg(ARM::PC) in EmitInstruction()
1253 .addReg(0) in EmitInstruction()
1255 .addReg(0)); in EmitInstruction()
1258 .addReg(MI->getOperand(0).getReg())); in EmitInstruction()
1288 .addImm(ARMCC::AL).addReg(0) in EmitInstruction()
1294 .addReg(ARM::LR) in EmitInstruction()
1295 .addReg(ARM::PC) in EmitInstruction()
1298 .addReg(0) in EmitInstruction()
1300 .addReg(0)); in EmitInstruction()
1303 .addReg(ARM::PC) in EmitInstruction()
1304 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
1307 .addReg(0) in EmitInstruction()
1309 .addReg(0)); in EmitInstruction()
1314 .addReg(ARM::LR) in EmitInstruction()
1315 .addReg(ARM::PC) in EmitInstruction()
1318 .addReg(0) in EmitInstruction()
1320 .addReg(0)); in EmitInstruction()
1331 .addReg(0)); in EmitInstruction()
1410 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
1411 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
1412 .addReg(ARM::PC) in EmitInstruction()
1415 .addReg(0)); in EmitInstruction()
1431 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
1432 .addReg(ARM::PC) in EmitInstruction()
1433 .addReg(MI->getOperand(1).getReg()) in EmitInstruction()
1436 .addReg(MI->getOperand(4).getReg()) in EmitInstruction()
1438 .addReg(0)); in EmitInstruction()
1475 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
1476 .addReg(ARM::PC) in EmitInstruction()
1477 .addReg(MI->getOperand(1).getReg()) in EmitInstruction()
1481 .addReg(MI->getOperand(4).getReg())); in EmitInstruction()
1512 .addReg(ARM::PC) in EmitInstruction()
1513 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
1516 .addReg(0)); in EmitInstruction()
1525 .addReg(ARM::PC) in EmitInstruction()
1526 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
1529 .addReg(0)); in EmitInstruction()
1540 .addReg(ARM::PC) in EmitInstruction()
1541 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
1544 .addReg(0)); in EmitInstruction()
1606 .addReg(ARM::PC) in EmitInstruction()
1607 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
1608 .addReg(MI->getOperand(1).getReg()) in EmitInstruction()
1611 .addReg(0) in EmitInstruction()
1613 .addReg(0)); in EmitInstruction()
1669 .addReg(ValReg) in EmitInstruction()
1670 .addReg(ARM::PC) in EmitInstruction()
1673 .addReg(0)); in EmitInstruction()
1676 .addReg(ValReg) in EmitInstruction()
1678 .addReg(ARM::CPSR) in EmitInstruction()
1679 .addReg(ValReg) in EmitInstruction()
1683 .addReg(0)); in EmitInstruction()
1686 .addReg(ValReg) in EmitInstruction()
1687 .addReg(SrcReg) in EmitInstruction()
1693 .addReg(0)); in EmitInstruction()
1696 .addReg(ARM::R0) in EmitInstruction()
1697 .addReg(ARM::CPSR) in EmitInstruction()
1701 .addReg(0)); in EmitInstruction()
1707 .addReg(0)); in EmitInstruction()
1711 .addReg(ARM::R0) in EmitInstruction()
1712 .addReg(ARM::CPSR) in EmitInstruction()
1716 .addReg(0)); in EmitInstruction()
1735 .addReg(ValReg) in EmitInstruction()
1736 .addReg(ARM::PC) in EmitInstruction()
1740 .addReg(0) in EmitInstruction()
1742 .addReg(0)); in EmitInstruction()
1745 .addReg(ValReg) in EmitInstruction()
1746 .addReg(SrcReg) in EmitInstruction()
1750 .addReg(0)); in EmitInstruction()
1753 .addReg(ARM::R0) in EmitInstruction()
1757 .addReg(0) in EmitInstruction()
1759 .addReg(0)); in EmitInstruction()
1762 .addReg(ARM::PC) in EmitInstruction()
1763 .addReg(ARM::PC) in EmitInstruction()
1767 .addReg(0) in EmitInstruction()
1769 .addReg(0)); in EmitInstruction()
1773 .addReg(ARM::R0) in EmitInstruction()
1777 .addReg(0) in EmitInstruction()
1779 .addReg(0)); in EmitInstruction()
1790 .addReg(ARM::SP) in EmitInstruction()
1791 .addReg(SrcReg) in EmitInstruction()
1795 .addReg(0)); in EmitInstruction()
1798 .addReg(ScratchReg) in EmitInstruction()
1799 .addReg(SrcReg) in EmitInstruction()
1803 .addReg(0)); in EmitInstruction()
1806 .addReg(ARM::R7) in EmitInstruction()
1807 .addReg(SrcReg) in EmitInstruction()
1811 .addReg(0)); in EmitInstruction()
1814 .addReg(ScratchReg) in EmitInstruction()
1817 .addReg(0)); in EmitInstruction()
1829 .addReg(ScratchReg) in EmitInstruction()
1830 .addReg(SrcReg) in EmitInstruction()
1836 .addReg(0)); in EmitInstruction()
1839 .addReg(ARM::SP) in EmitInstruction()
1840 .addReg(ScratchReg) in EmitInstruction()
1843 .addReg(0)); in EmitInstruction()
1846 .addReg(ScratchReg) in EmitInstruction()
1847 .addReg(SrcReg) in EmitInstruction()
1851 .addReg(0)); in EmitInstruction()
1854 .addReg(ARM::R7) in EmitInstruction()
1855 .addReg(SrcReg) in EmitInstruction()
1859 .addReg(0)); in EmitInstruction()
1862 .addReg(ScratchReg) in EmitInstruction()
1865 .addReg(0)); in EmitInstruction()