Lines Matching refs:DestReg
696 unsigned DestReg, bool KillSrc, in copyFromCPSR() argument
703 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg); in copyFromCPSR()
739 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
741 bool GPRDest = ARM::GPRRegClass.contains(DestReg); in copyPhysReg()
745 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) in copyPhysReg()
750 bool SPRDest = ARM::SPRRegClass.contains(DestReg); in copyPhysReg()
760 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP()) in copyPhysReg()
762 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
766 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); in copyPhysReg()
780 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
784 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
789 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
793 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
797 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
801 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
805 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
810 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
815 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
820 } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.isFPOnlySP()) { in copyPhysReg()
825 copyFromCPSR(MBB, I, DestReg, KillSrc, Subtarget); in copyPhysReg()
827 } else if (DestReg == ARM::CPSR) { in copyPhysReg()
838 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { in copyPhysReg()
846 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing); in copyPhysReg()
863 Mov->addRegisterDefined(DestReg, TRI); in copyPhysReg()
1073 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
1091 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) in loadRegFromStackSlot()
1095 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) in loadRegFromStackSlot()
1102 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) in loadRegFromStackSlot()
1109 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1110 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1119 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1120 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1123 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
1124 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1131 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) in loadRegFromStackSlot()
1135 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) in loadRegFromStackSlot()
1145 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg) in loadRegFromStackSlot()
1153 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1154 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1155 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1156 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
1157 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1165 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) in loadRegFromStackSlot()
1173 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1174 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1175 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1176 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1177 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
1178 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1189 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1190 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1191 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1192 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1193 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1194 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1195 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1196 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1197 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
1198 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1391 unsigned DestReg, unsigned SubIdx, in reMaterialize() argument
1398 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); in reMaterialize()
1408 DestReg) in reMaterialize()
1856 unsigned DestReg = MI->getOperand(0).getReg(); in optimizeSelect() local
1858 if (!MRI.constrainRegClass(DestReg, PreviousClass)) in optimizeSelect()
1864 DefMI->getDesc(), DestReg); in optimizeSelect()
1947 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitARMRegPlusImmediate() argument
1950 if (NumBytes == 0 && DestReg != BaseReg) { in emitARMRegPlusImmediate()
1951 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg) in emitARMRegPlusImmediate()
1973 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) in emitARMRegPlusImmediate()
1977 BaseReg = DestReg; in emitARMRegPlusImmediate()