397   MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
399     MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
401     MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
403     MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
434   MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandVLD()
530     MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
532       MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
534       MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
536       MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
578     MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandLaneOp()
673       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
703     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
962         .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
1012             .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
1053         .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
1104       MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
1105         .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandMI()
1108       MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandMI()