Lines Matching refs:Op0IsKill
110 unsigned Op0, bool Op0IsKill);
113 unsigned Op0, bool Op0IsKill,
117 unsigned Op0, bool Op0IsKill,
122 unsigned Op0, bool Op0IsKill,
126 unsigned Op0, bool Op0IsKill,
288 unsigned Op0, bool Op0IsKill) { in fastEmitInst_r() argument
297 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill)); in fastEmitInst_r()
300 .addReg(Op0, Op0IsKill * RegState::Kill)); in fastEmitInst_r()
310 unsigned Op0, bool Op0IsKill, in fastEmitInst_rr() argument
323 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rr()
327 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rr()
338 unsigned Op0, bool Op0IsKill, in fastEmitInst_rrr() argument
353 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rrr()
358 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rrr()
370 unsigned Op0, bool Op0IsKill, in fastEmitInst_ri() argument
381 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_ri()
385 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_ri()
396 unsigned Op0, bool Op0IsKill, in fastEmitInst_rri() argument
409 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rri()
414 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rri()