297                             ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));  in fastEmitInst_r()
300                    .addReg(Op0, Op0IsKill * RegState::Kill));  in fastEmitInst_r()
323             .addReg(Op0, Op0IsKill * RegState::Kill)  in fastEmitInst_rr()
324             .addReg(Op1, Op1IsKill * RegState::Kill));  in fastEmitInst_rr()
327                    .addReg(Op0, Op0IsKill * RegState::Kill)  in fastEmitInst_rr()
328                    .addReg(Op1, Op1IsKill * RegState::Kill));  in fastEmitInst_rr()
353             .addReg(Op0, Op0IsKill * RegState::Kill)  in fastEmitInst_rrr()
354             .addReg(Op1, Op1IsKill * RegState::Kill)  in fastEmitInst_rrr()
355             .addReg(Op2, Op2IsKill * RegState::Kill));  in fastEmitInst_rrr()
358                    .addReg(Op0, Op0IsKill * RegState::Kill)  in fastEmitInst_rrr()
359                    .addReg(Op1, Op1IsKill * RegState::Kill)  in fastEmitInst_rrr()
360                    .addReg(Op2, Op2IsKill * RegState::Kill));  in fastEmitInst_rrr()
381             .addReg(Op0, Op0IsKill * RegState::Kill)  in fastEmitInst_ri()
385                    .addReg(Op0, Op0IsKill * RegState::Kill)  in fastEmitInst_ri()
409             .addReg(Op0, Op0IsKill * RegState::Kill)  in fastEmitInst_rri()
410             .addReg(Op1, Op1IsKill * RegState::Kill)  in fastEmitInst_rri()
414                    .addReg(Op0, Op0IsKill * RegState::Kill)  in fastEmitInst_rri()
415                    .addReg(Op1, Op1IsKill * RegState::Kill)  in fastEmitInst_rri()
2000                       .addReg(NextVA.getLocReg(), RegState::Define)  in ProcessCallArgs()
2158     MIB.addReg(RetRegs[i], RegState::Implicit);  in SelectRet()
2264     MIB.addReg(RegArgs[i], RegState::Implicit);  in ARMEmitLibcall()
2415     MIB.addReg(RegArgs[i], RegState::Implicit);  in SelectCall()
2717       MIB.addReg(ARM::CPSR, RegState::Define);  in ARMEmitIntExt()
2719     AddDefaultPred(MIB.addReg(SrcReg, isKill * RegState::Kill).addImm(ImmEnc));  in ARMEmitIntExt()