1438   unsigned SrcReg1 = getRegForValue(Src1Value);  in ARMEmitCmp()  local
1439   if (SrcReg1 == 0) return false;  in ARMEmitCmp()
1449     SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);  in ARMEmitCmp()
1450     if (SrcReg1 == 0) return false;  in ARMEmitCmp()
1458   SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);  in ARMEmitCmp()
1462                     .addReg(SrcReg1).addReg(SrcReg2));  in ARMEmitCmp()
1466       .addReg(SrcReg1);  in ARMEmitCmp()
1774   unsigned SrcReg1 = getRegForValue(I->getOperand(0));  in SelectBinaryIntOp()  local
1775   if (SrcReg1 == 0) return false;  in SelectBinaryIntOp()
1783   SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);  in SelectBinaryIntOp()
1787                   .addReg(SrcReg1).addReg(SrcReg2));  in SelectBinaryIntOp()