Lines Matching refs:addReg
297 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill)); in fastEmitInst_r()
300 .addReg(Op0, Op0IsKill * RegState::Kill)); in fastEmitInst_r()
303 .addReg(II.ImplicitDefs[0])); in fastEmitInst_r()
323 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rr()
324 .addReg(Op1, Op1IsKill * RegState::Kill)); in fastEmitInst_rr()
327 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rr()
328 .addReg(Op1, Op1IsKill * RegState::Kill)); in fastEmitInst_rr()
331 .addReg(II.ImplicitDefs[0])); in fastEmitInst_rr()
353 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rrr()
354 .addReg(Op1, Op1IsKill * RegState::Kill) in fastEmitInst_rrr()
355 .addReg(Op2, Op2IsKill * RegState::Kill)); in fastEmitInst_rrr()
358 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rrr()
359 .addReg(Op1, Op1IsKill * RegState::Kill) in fastEmitInst_rrr()
360 .addReg(Op2, Op2IsKill * RegState::Kill)); in fastEmitInst_rrr()
363 .addReg(II.ImplicitDefs[0])); in fastEmitInst_rrr()
381 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_ri()
385 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_ri()
389 .addReg(II.ImplicitDefs[0])); in fastEmitInst_ri()
409 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rri()
410 .addReg(Op1, Op1IsKill * RegState::Kill) in fastEmitInst_rri()
414 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rri()
415 .addReg(Op1, Op1IsKill * RegState::Kill) in fastEmitInst_rri()
419 .addReg(II.ImplicitDefs[0])); in fastEmitInst_rri()
438 .addReg(II.ImplicitDefs[0])); in fastEmitInst_i()
451 .addReg(SrcReg)); in ARMMoveToFPReg()
461 .addReg(SrcReg)); in ARMMoveToIntReg()
507 .addReg(0)); in ARMMaterializeFP()
659 .addReg(DestReg) in ARMMaterializeGV()
673 .addReg(DestReg) in ARMMaterializeGV()
678 .addReg(DestReg) in ARMMaterializeGV()
939 MIB.addReg(0); in AddLoadStoreOperands()
947 MIB.addReg(Addr.Base.Reg); in AddLoadStoreOperands()
953 MIB.addReg(0); in AddLoadStoreOperands()
1058 .addReg(ResultReg)); in ARMEmitLoad()
1099 .addReg(SrcReg).addImm(1)); in ARMEmitStore()
1146 .addReg(SrcReg)); in ARMEmitStore()
1171 .addReg(SrcReg); in ARMEmitStore()
1281 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR); in SelectBranch()
1295 .addReg(OpReg).addImm(1)); in SelectBranch()
1305 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); in SelectBranch()
1333 .addReg(CmpReg) in SelectBranch()
1344 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); in SelectBranch()
1356 TII.get(Opc)).addReg(AddrReg)); in SelectIndirectBr()
1462 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1466 .addReg(SrcReg1); in ARMEmitCmp()
1505 .addReg(ZeroReg).addImm(1) in SelectCmp()
1506 .addImm(ARMPred).addReg(ARM::CPSR); in SelectCmp()
1526 .addReg(Op)); in SelectFPExt()
1545 .addReg(Op)); in SelectFPTrunc()
1589 TII.get(Opc), ResultReg).addReg(FP)); in SelectIToFP()
1615 TII.get(Opc), ResultReg).addReg(Op)); in SelectFPToI()
1664 .addReg(CondReg) in SelectSelect()
1685 .addReg(Op2Reg) in SelectSelect()
1686 .addReg(Op1Reg) in SelectSelect()
1688 .addReg(ARM::CPSR); in SelectSelect()
1693 .addReg(Op1Reg) in SelectSelect()
1696 .addReg(ARM::CPSR); in SelectSelect()
1787 .addReg(SrcReg1).addReg(SrcReg2)); in SelectBinaryIntOp()
1829 .addReg(Op1).addReg(Op2)); in SelectBinaryFPOp()
1986 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg); in ProcessCallArgs()
2000 .addReg(NextVA.getLocReg(), RegState::Define) in ProcessCallArgs()
2001 .addReg(Arg)); in ProcessCallArgs()
2049 .addReg(RVLocs[0].getLocReg()) in FinishCall()
2050 .addReg(RVLocs[1].getLocReg())); in FinishCall()
2070 ResultReg).addReg(RVLocs[0].getLocReg()); in FinishCall()
2147 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg); in SelectRet()
2158 MIB.addReg(RetRegs[i], RegState::Implicit); in SelectRet()
2258 MIB.addReg(CalleeReg); in ARMEmitLibcall()
2264 MIB.addReg(RegArgs[i], RegState::Implicit); in ARMEmitLibcall()
2407 MIB.addReg(CalleeReg); in SelectCall()
2415 MIB.addReg(RegArgs[i], RegState::Implicit); in SelectCall()
2507 .addReg(SrcReg).addImm(0)); in SelectIntrinsicCall()
2717 MIB.addReg(ARM::CPSR, RegState::Define); in ARMEmitIntExt()
2719 AddDefaultPred(MIB.addReg(SrcReg, isKill * RegState::Kill).addImm(ImmEnc)); in ARMEmitIntExt()
2795 .addReg(Reg1); in SelectShift()
2800 MIB.addReg(Reg2); in SelectShift()
2979 .addReg(DestReg1) in ARMLowerPICELF()
2980 .addReg(GlobalBaseReg); in ARMLowerPICELF()
3054 ResultReg).addReg(DstReg, getKillRegState(true)); in fastLowerArguments()