294   Op0 = constrainOperandRegClass(II, Op0, 1);  in fastEmitInst_r()
317   Op0 = constrainOperandRegClass(II, Op0, 1);  in fastEmitInst_rr()
318   Op1 = constrainOperandRegClass(II, Op1, 2);  in fastEmitInst_rr()
346   Op0 = constrainOperandRegClass(II, Op0, 1);  in fastEmitInst_rrr()
347   Op1 = constrainOperandRegClass(II, Op1, 2);  in fastEmitInst_rrr()
348   Op2 = constrainOperandRegClass(II, Op1, 3);  in fastEmitInst_rrr()
377   Op0 = constrainOperandRegClass(II, Op0, 1);  in fastEmitInst_ri()
404   Op0 = constrainOperandRegClass(II, Op0, 1);  in fastEmitInst_rri()
405   Op1 = constrainOperandRegClass(II, Op1, 2);  in fastEmitInst_rri()
572     ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0);  in ARMMaterializeInt()
646       DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);  in ARMMaterializeGV()
722     ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);  in fastMaterializeAlloca()
1096       SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);  in ARMEmitStore()
1168   SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0);  in ARMEmitStore()
1292       OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);  in SelectBranch()
1330   CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0);  in SelectBranch()
1458   SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);  in ARMEmitCmp()
1460     SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);  in ARMEmitCmp()
1661   CondReg = constrainOperandRegClass(TII.get(CmpOpc), CondReg, 0);  in SelectSelect()
1681     Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);  in SelectSelect()
1682     Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);  in SelectSelect()
1690     Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);  in SelectSelect()
1783   SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);  in SelectBinaryIntOp()
1784   SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);  in SelectBinaryIntOp()
2718     SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);  in ARMEmitIntExt()
2953     DestReg1 = constrainOperandRegClass(TII.get(ARM::t2LDRpci), DestReg1, 0);  in ARMLowerPICELF()
2960     DestReg1 = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg1, 0);  in ARMLowerPICELF()
2974   DestReg2 = constrainOperandRegClass(TII.get(Opc), DestReg2, 0);  in ARMLowerPICELF()
2975   DestReg1 = constrainOperandRegClass(TII.get(Opc), DestReg1, 1);  in ARMLowerPICELF()
2976   GlobalBaseReg = constrainOperandRegClass(TII.get(Opc), GlobalBaseReg, 2);  in ARMLowerPICELF()