2637         /*  1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  31 },  in ARMEmitIntExt()
2638         /*  1 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  31 } },  in ARMEmitIntExt()
2639         /*  8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  24 },  in ARMEmitIntExt()
2640         /*  8 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  24 } },  in ARMEmitIntExt()
2641         /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  16 },  in ARMEmitIntExt()
2642         /* 16 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  16 } }  in ARMEmitIntExt()
2647         /*  1 bit sext */ { { ARM::KILL   , 0, ARM_AM::no_shift,   0 },  in ARMEmitIntExt()
2648         /*  1 bit zext */   { ARM::ANDri  , 1, ARM_AM::no_shift,   1 } },  in ARMEmitIntExt()
2649         /*  8 bit sext */ { { ARM::SXTB   , 0, ARM_AM::no_shift,   0 },  in ARMEmitIntExt()
2650         /*  8 bit zext */   { ARM::ANDri  , 1, ARM_AM::no_shift, 255 } },  in ARMEmitIntExt()
2651         /* 16 bit sext */ { { ARM::SXTH   , 0, ARM_AM::no_shift,   0 },  in ARMEmitIntExt()
2652         /* 16 bit zext */   { ARM::UXTH   , 0, ARM_AM::no_shift,   0 } }  in ARMEmitIntExt()
2655         /*  1 bit sext */ { { ARM::KILL   , 0, ARM_AM::no_shift,   0 },  in ARMEmitIntExt()
2656         /*  1 bit zext */   { ARM::t2ANDri, 1, ARM_AM::no_shift,   1 } },  in ARMEmitIntExt()
2657         /*  8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift,   0 },  in ARMEmitIntExt()
2658         /*  8 bit zext */   { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },  in ARMEmitIntExt()
2659         /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift,   0 },  in ARMEmitIntExt()
2660         /* 16 bit zext */   { ARM::t2UXTH , 0, ARM_AM::no_shift,   0 } }  in ARMEmitIntExt()
2685   assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&  in ARMEmitIntExt()
2696   bool ImmIsSO = (Shift != ARM_AM::no_shift);  in ARMEmitIntExt()