251                          .addImm(~AlignMask));  in emitAligningInstructions()
256                              .addImm(AlignMask)));  in emitAligningInstructions()
265               .addImm(ARM_AM::getSORegOpc(ARM_AM::lsr, NrBitsToZero))));  in emitAligningInstructions()
269               .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, NrBitsToZero))));  in emitAligningInstructions()
277                        .addImm(~AlignMask));  in emitAligningInstructions()
441                      .addImm(NumWords)  in emitPrologue()
445         .addImm(NumWords)  in emitPrologue()
454         .addImm((unsigned)ARMCC::AL).addReg(0)  in emitPrologue()
466         .addImm((unsigned)ARMCC::AL).addReg(0)  in emitPrologue()
669         .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);  in emitPrologue()
716     if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);  in fixTCReturn()
806             .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);  in emitEpilogue()
994         .addImm(-4);  in emitPushInst()
1080         MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));  in emitPopInst()
1082         MIB.addImm(4);  in emitPopInst()
1145                                   .addImm(8 * NumAlignedDPRCS2Regs)));  in emitAlignedDPRCS2Spills()
1178                    .addReg(ARM::R4, RegState::Kill).addImm(16)  in emitAlignedDPRCS2Spills()
1195                    .addReg(ARM::R4).addImm(16).addReg(NextReg)  in emitAlignedDPRCS2Spills()
1207                    .addReg(ARM::R4).addImm(16).addReg(SupReg));  in emitAlignedDPRCS2Spills()
1218                    .addReg(ARM::R4).addImm((NextReg-R4BaseReg)*2));  in emitAlignedDPRCS2Spills()
1284                               .addFrameIndex(D8SpillFI).addImm(0)));  in emitAlignedDPRCS2Restores()
1295                    .addReg(ARM::R4, RegState::Kill).addImm(16)  in emitAlignedDPRCS2Restores()
1310                    .addReg(ARM::R4).addImm(16)  in emitAlignedDPRCS2Restores()
1321                    .addReg(ARM::R4).addImm(16));  in emitAlignedDPRCS2Restores()
1329                    .addReg(ARM::R4).addImm(2*(NextReg-R4BaseReg)));  in emitAlignedDPRCS2Restores()
1972             .addReg(ScratchReg1).addImm(AlignedStackSize));  in adjustForSegmentedStacks()
1975                       .addReg(ARM::SP).addImm(AlignedStackSize)).addReg(0);  in adjustForSegmentedStacks()
1991                       .addReg(ScratchReg0).addImm(0));  in adjustForSegmentedStacks()
1996                      .addImm(15)  in adjustForSegmentedStacks()
1997                      .addImm(0)  in adjustForSegmentedStacks()
1998                      .addImm(13)  in adjustForSegmentedStacks()
1999                      .addImm(0)  in adjustForSegmentedStacks()
2000                      .addImm(3));  in adjustForSegmentedStacks()
2009                       .addReg(ScratchReg0).addImm(4 * TlsOffset));  in adjustForSegmentedStacks()
2022        .addImm(ARMCC::LO)  in adjustForSegmentedStacks()
2034                                         ScratchReg0)).addImm(AlignedStackSize));  in adjustForSegmentedStacks()
2037                       .addImm(AlignedStackSize)).addReg(0);  in adjustForSegmentedStacks()
2044             .addImm(alignToARMConstant(ARMFI->getArgumentStackSize())));  in adjustForSegmentedStacks()
2047                    .addImm(alignToARMConstant(ARMFI->getArgumentStackSize())))  in adjustForSegmentedStacks()
2094                      .addImm(4));  in adjustForSegmentedStacks()