Lines Matching refs:Ops
1498 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG), in SelectARMIndexedLoad() local
1501 MVT::i32, MVT::Other, Ops); in SelectARMIndexedLoad()
1505 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG), in SelectARMIndexedLoad() local
1508 MVT::i32, MVT::Other, Ops); in SelectARMIndexedLoad()
1554 SDValue Ops[]= { Base, Offset, getAL(CurDAG), in SelectT2IndexedLoad() local
1557 MVT::Other, Ops); in SelectT2IndexedLoad()
1570 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode() local
1571 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createGPRPairNode()
1581 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createSRegPairNode() local
1582 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createSRegPairNode()
1591 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createDRegPairNode() local
1592 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createDRegPairNode()
1601 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createQRegPairNode() local
1602 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQRegPairNode()
1615 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadSRegsNode() local
1617 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQuadSRegsNode()
1629 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadDRegsNode() local
1631 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQuadDRegsNode()
1643 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadQRegsNode() local
1645 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQuadQRegsNode()
1827 SmallVector<SDValue, 7> Ops; in SelectVLD() local
1833 Ops.push_back(MemAddr); in SelectVLD()
1834 Ops.push_back(Align); in SelectVLD()
1845 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc); in SelectVLD()
1847 Ops.push_back(Pred); in SelectVLD()
1848 Ops.push_back(Reg0); in SelectVLD()
1849 Ops.push_back(Chain); in SelectVLD()
1850 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVLD()
1867 Ops.push_back(SDValue(VLdA, 1)); in SelectVLD()
1868 Ops.push_back(Align); in SelectVLD()
1874 Ops.push_back(Reg0); in SelectVLD()
1876 Ops.push_back(SDValue(VLdA, 0)); in SelectVLD()
1877 Ops.push_back(Pred); in SelectVLD()
1878 Ops.push_back(Reg0); in SelectVLD()
1879 Ops.push_back(Chain); in SelectVLD()
1880 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, Ops); in SelectVLD()
1953 SmallVector<SDValue, 7> Ops; in SelectVST() local
1984 Ops.push_back(MemAddr); in SelectVST()
1985 Ops.push_back(Align); in SelectVST()
1995 Ops.push_back(Inc); in SelectVST()
1997 Ops.push_back(Reg0); in SelectVST()
1999 Ops.push_back(SrcReg); in SelectVST()
2000 Ops.push_back(Pred); in SelectVST()
2001 Ops.push_back(Reg0); in SelectVST()
2002 Ops.push_back(Chain); in SelectVST()
2003 SDNode *VSt = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVST()
2033 Ops.push_back(SDValue(VStA, 0)); in SelectVST()
2034 Ops.push_back(Align); in SelectVST()
2040 Ops.push_back(Reg0); in SelectVST()
2042 Ops.push_back(RegSeq); in SelectVST()
2043 Ops.push_back(Pred); in SelectVST()
2044 Ops.push_back(Reg0); in SelectVST()
2045 Ops.push_back(Chain); in SelectVST()
2047 Ops); in SelectVST()
2118 SmallVector<SDValue, 8> Ops; in SelectVLDSTLane() local
2119 Ops.push_back(MemAddr); in SelectVLDSTLane()
2120 Ops.push_back(Align); in SelectVLDSTLane()
2123 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc); in SelectVLDSTLane()
2144 Ops.push_back(SuperReg); in SelectVLDSTLane()
2145 Ops.push_back(getI32Imm(Lane)); in SelectVLDSTLane()
2146 Ops.push_back(Pred); in SelectVLDSTLane()
2147 Ops.push_back(Reg0); in SelectVLDSTLane()
2148 Ops.push_back(Chain); in SelectVLDSTLane()
2152 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVLDSTLane()
2215 SmallVector<SDValue, 6> Ops; in SelectVLDDup() local
2216 Ops.push_back(MemAddr); in SelectVLDDup()
2217 Ops.push_back(Align); in SelectVLDDup()
2223 Ops.push_back(Inc); in SelectVLDDup()
2226 Ops.push_back(Reg0); in SelectVLDDup()
2228 Ops.push_back(Pred); in SelectVLDDup()
2229 Ops.push_back(Reg0); in SelectVLDDup()
2230 Ops.push_back(Chain); in SelectVLDDup()
2238 SDNode *VLdDup = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVLDDup()
2277 SmallVector<SDValue, 6> Ops; in SelectVTBL() local
2279 Ops.push_back(N->getOperand(1)); in SelectVTBL()
2280 Ops.push_back(RegSeq); in SelectVTBL()
2281 Ops.push_back(N->getOperand(FirstTblReg + NumVecs)); in SelectVTBL()
2282 Ops.push_back(getAL(CurDAG)); // predicate in SelectVTBL()
2283 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register in SelectVTBL()
2284 return CurDAG->getMachineNode(Opc, dl, VT, Ops); in SelectVTBL()
2320 SDValue Ops[] = { N->getOperand(0).getOperand(0), in SelectV6T2BitfieldExtractOp() local
2323 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in SelectV6T2BitfieldExtractOp()
2331 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc, in SelectV6T2BitfieldExtractOp() local
2333 return CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops); in SelectV6T2BitfieldExtractOp()
2336 SDValue Ops[] = { N->getOperand(0).getOperand(0), in SelectV6T2BitfieldExtractOp() local
2340 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in SelectV6T2BitfieldExtractOp()
2359 SDValue Ops[] = { N->getOperand(0).getOperand(0), in SelectV6T2BitfieldExtractOp() local
2363 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in SelectV6T2BitfieldExtractOp()
2378 SDValue Ops[] = { N->getOperand(0).getOperand(0), in SelectV6T2BitfieldExtractOp() local
2382 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in SelectV6T2BitfieldExtractOp()
2489 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; in Select() local
2491 Ops); in Select()
2493 SDValue Ops[] = { in Select() local
2501 Ops); in Select()
2525 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32), in Select() local
2528 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in Select()
2555 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; in Select() local
2556 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops); in Select()
2558 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; in Select() local
2559 return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops); in Select()
2571 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; in Select() local
2572 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops); in Select()
2574 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; in Select() local
2575 return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops); in Select()
2614 SDValue Ops[] = { N0.getOperand(0), Imm16, in Select() local
2616 return CurDAG->getMachineNode(Opc, dl, VT, Ops); in Select()
2629 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
2631 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops); in Select()
2633 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
2638 dl, MVT::i32, MVT::i32, Ops); in Select()
2645 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
2647 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops); in Select()
2649 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
2654 dl, MVT::i32, MVT::i32, Ops); in Select()
2659 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), in Select() local
2662 return CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops); in Select()
2664 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), in Select() local
2670 dl, MVT::i32, MVT::i32, Ops); in Select()
2675 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), in Select() local
2678 return CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops); in Select()
2680 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), in Select() local
2686 dl, MVT::i32, MVT::i32, Ops); in Select()
2727 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag }; in Select() local
2729 MVT::Glue, Ops); in Select()
2756 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select() local
2757 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops); in Select()
2776 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select() local
2777 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops); in Select()
2795 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select() local
2796 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops); in Select()
3039 SmallVector<SDValue, 7> Ops; in Select() local
3040 Ops.push_back(MemAddr); in Select()
3041 Ops.push_back(getAL(CurDAG)); in Select()
3042 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in Select()
3043 Ops.push_back(Chain); in Select()
3044 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops); in Select()
3093 SmallVector<SDValue, 7> Ops; in Select() local
3095 Ops.push_back(Val0); in Select()
3096 Ops.push_back(Val1); in Select()
3099 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0)); in Select()
3100 Ops.push_back(MemAddr); in Select()
3101 Ops.push_back(getAL(CurDAG)); in Select()
3102 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in Select()
3103 Ops.push_back(Chain); in Select()
3109 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops); in Select()
3289 SmallVector<SDValue, 6> Ops; in Select() local
3291 Ops.push_back(N->getOperand(0)); in Select()
3292 Ops.push_back(N->getOperand(1)); in Select()
3293 Ops.push_back(getAL(CurDAG)); // Predicate in Select()
3294 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register in Select()
3295 return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops); in Select()
3306 SmallVector<SDValue, 6> Ops; in Select() local
3307 Ops.push_back(RegSeq); in Select()
3308 Ops.push_back(N->getOperand(2)); in Select()
3309 Ops.push_back(getAL(CurDAG)); // Predicate in Select()
3310 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register in Select()
3311 return CurDAG->getMachineNode(ARM::VTBL2, dl, VT, Ops); in Select()
3417 std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1); in SelectInlineAsm() local
3418 Ops.push_back(T1.getValue(1)); in SelectInlineAsm()
3419 CurDAG->UpdateNodeOperands(GU, Ops); in SelectInlineAsm()