Lines Matching refs:ArgLocs
1497 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall() local
1498 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCall()
1524 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); in LowerCall()
1527 CCValAssign &VA = ArgLocs[i]; in LowerCall()
1559 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); in LowerCall()
1561 VA = ArgLocs[++i]; // skip ahead to next loc in LowerCall()
1564 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); in LowerCall()
1572 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], in LowerCall()
2081 SmallVector<CCValAssign, 16> ArgLocs; in IsEligibleForTailCallOptimization() local
2082 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs, in IsEligibleForTailCallOptimization()
2094 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); in IsEligibleForTailCallOptimization()
2097 CCValAssign &VA = ArgLocs[i]; in IsEligibleForTailCallOptimization()
2110 if (!ArgLocs[++i].isRegLoc()) in IsEligibleForTailCallOptimization()
2113 if (!ArgLocs[++i].isRegLoc()) in IsEligibleForTailCallOptimization()
2115 if (!ArgLocs[++i].isRegLoc()) in IsEligibleForTailCallOptimization()
2930 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments() local
2931 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerFormalArguments()
2953 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerFormalArguments()
2957 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments()
2982 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerFormalArguments()
2983 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments()
2997 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i], in LowerFormalArguments()
2999 VA = ArgLocs[++i]; // skip ahead to next loc in LowerFormalArguments()
3008 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], in LowerFormalArguments()
3017 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); in LowerFormalArguments()