Lines Matching refs:VA
1345 CCValAssign VA = RVLocs[i]; in LowerCallResult() local
1350 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 && in LowerCallResult()
1357 if (VA.needsCustom()) { in LowerCallResult()
1359 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1363 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1364 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1372 if (VA.getLocVT() == MVT::v2f64) { in LowerCallResult()
1377 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1378 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1381 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1382 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1392 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), in LowerCallResult()
1398 switch (VA.getLocInfo()) { in LowerCallResult()
1402 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); in LowerCallResult()
1417 const CCValAssign &VA, in LowerMemOpCallTo() argument
1419 unsigned LocMemOffset = VA.getLocMemOffset(); in LowerMemOpCallTo()
1430 CCValAssign &VA, CCValAssign &NextVA, in PassF64ArgInRegs() argument
1438 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id))); in PassF64ArgInRegs()
1527 CCValAssign &VA = ArgLocs[i]; in LowerCall() local
1533 switch (VA.getLocInfo()) { in LowerCall()
1537 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1540 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1543 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1546 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall()
1551 if (VA.needsCustom()) { in LowerCall()
1552 if (VA.getLocVT() == MVT::v2f64) { in LowerCall()
1559 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); in LowerCall()
1561 VA = ArgLocs[++i]; // skip ahead to next loc in LowerCall()
1562 if (VA.isRegLoc()) { in LowerCall()
1564 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); in LowerCall()
1566 assert(VA.isMemLoc()); in LowerCall()
1569 dl, DAG, VA, Flags)); in LowerCall()
1572 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], in LowerCall()
1575 } else if (VA.isRegLoc()) { in LowerCall()
1577 assert(VA.getLocVT() == MVT::i32 && in LowerCall()
1583 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
1585 assert(VA.isMemLoc()); in LowerCall()
1619 unsigned LocMemOffset = VA.getLocMemOffset(); in LowerCall()
1635 assert(VA.isMemLoc()); in LowerCall()
1638 dl, DAG, VA, Flags)); in LowerCall()
2097 CCValAssign &VA = ArgLocs[i]; in IsEligibleForTailCallOptimization() local
2098 EVT RegVT = VA.getLocVT(); in IsEligibleForTailCallOptimization()
2101 if (VA.getLocInfo() == CCValAssign::Indirect) in IsEligibleForTailCallOptimization()
2103 if (VA.needsCustom()) { in IsEligibleForTailCallOptimization()
2108 if (!VA.isRegLoc()) in IsEligibleForTailCallOptimization()
2118 } else if (!VA.isRegLoc()) { in IsEligibleForTailCallOptimization()
2119 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, in IsEligibleForTailCallOptimization()
2204 CCValAssign &VA = RVLocs[i]; in LowerReturn() local
2205 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
2209 switch (VA.getLocInfo()) { in LowerReturn()
2213 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerReturn()
2217 if (VA.needsCustom()) { in LowerReturn()
2218 if (VA.getLocVT() == MVT::v2f64) { in LowerReturn()
2225 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
2229 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2230 VA = RVLocs[++i]; // skip ahead to next loc in LowerReturn()
2231 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
2235 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2236 VA = RVLocs[++i]; // skip ahead to next loc in LowerReturn()
2246 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
2250 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2251 VA = RVLocs[++i]; // skip ahead to next loc in LowerReturn()
2252 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
2256 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); in LowerReturn()
2261 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2796 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, in GetF64FormalArgument() argument
2809 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in GetF64FormalArgument()
2957 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments() local
2958 unsigned Index = VA.getValNo(); in LowerFormalArguments()
2963 assert(VA.isMemLoc() && "unexpected byval pointer in reg"); in LowerFormalArguments()
2983 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments() local
2984 if (Ins[VA.getValNo()].isOrigArg()) { in LowerFormalArguments()
2986 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx); in LowerFormalArguments()
2987 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex(); in LowerFormalArguments()
2990 if (VA.isRegLoc()) { in LowerFormalArguments()
2991 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
2993 if (VA.needsCustom()) { in LowerFormalArguments()
2996 if (VA.getLocVT() == MVT::v2f64) { in LowerFormalArguments()
2997 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i], in LowerFormalArguments()
2999 VA = ArgLocs[++i]; // skip ahead to next loc in LowerFormalArguments()
3001 if (VA.isMemLoc()) { in LowerFormalArguments()
3002 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true); in LowerFormalArguments()
3008 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], in LowerFormalArguments()
3017 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); in LowerFormalArguments()
3035 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
3042 switch (VA.getLocInfo()) { in LowerFormalArguments()
3046 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
3050 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
3051 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
3055 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
3056 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
3065 assert(VA.isMemLoc()); in LowerFormalArguments()
3066 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered"); in LowerFormalArguments()
3068 int index = VA.getValNo(); in LowerFormalArguments()
3086 CurByValIndex, VA.getLocMemOffset(), in LowerFormalArguments()
3091 unsigned FIOffset = VA.getLocMemOffset(); in LowerFormalArguments()
3092 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8, in LowerFormalArguments()
3097 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, in LowerFormalArguments()