Lines Matching refs:EXTRACT_SUBREG
4171 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4177 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4183 (v2f32 (EXTRACT_SUBREG QPR:$src2,
4209 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4216 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4231 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4238 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4288 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4296 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4305 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4374 (v4i16 (EXTRACT_SUBREG
4386 (v2i32 (EXTRACT_SUBREG
4443 (v4i16 (EXTRACT_SUBREG
4455 (v2i32 (EXTRACT_SUBREG
4506 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4514 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4522 (v2f32 (EXTRACT_SUBREG QPR:$src3,
5597 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5601 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5605 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5609 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5613 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
5619 (i32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5623 (i32 (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5626 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
5629 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
5632 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5634 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5670 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
5676 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
5682 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
5805 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
5809 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
5813 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
5817 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
6004 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
6249 (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG
6282 (EXTRACT_SUBREG
6290 (EXTRACT_SUBREG
6301 (EXTRACT_SUBREG
6315 (f32 (EXTRACT_SUBREG
6323 (i32 (EXTRACT_SUBREG
6351 (VSITOD (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6353 (VSITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6355 (VUITOD (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6357 (VUITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6362 (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>,
6512 (f32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6544 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
6551 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6556 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6561 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # InsnLanes # InsnTy)
6574 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6580 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6586 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # InsnLanes # InsnTy)
6597 // (EXTRACT_SUBREG (VMOVLuv4i32
6598 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
6609 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6615 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6621 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6636 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6643 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6650 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6662 // (EXTRACT_SUBREG (VMOVLuv4i32
6663 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd16 addrmode6:$addr,
6672 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6673 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6679 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6680 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6686 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
6687 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6702 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6703 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6710 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6711 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6718 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
6719 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6757 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6761 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6765 (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16
6774 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6779 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6784 (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16