Lines Matching refs:QPR
630 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
632 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
636 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
640 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1031 : PseudoNLdSt<(outs QPR:$dst),
1032 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1035 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1036 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1081 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
1105 def : Pat<(vector_insert (v4f32 QPR:$src),
1107 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1619 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1622 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1626 (ins addrmode6:$addr, QPR:$src), itin,
1630 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
2033 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
2037 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
2066 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2092 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
2093 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
2109 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2374 def : Pat<(dword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2375 (VST1q64 addrmode6:$addr, QPR:$value)>;
2378 def : Pat<(word_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2379 (VST1q32 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2382 def : Pat<(hword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2383 (VST1q16 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2386 def : Pat<(byte_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2387 (VST1q8 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2442 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2443 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2444 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2458 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2459 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2460 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2473 : N2Vnp<0b10, op17_16, op10_8, op7, 1, (outs QPR:$Vd), (ins QPR:$Vm),
2475 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2481 : N2Vnp<op19_18, op17_16, op10_8, op7, op6, (outs QPR:$Vd), (ins QPR:$Vm),
2483 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2490 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vm),
2492 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vm))))]> {
2502 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2503 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2511 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2512 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2519 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2521 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2528 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2530 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2540 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2541 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2600 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2602 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2611 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2613 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2622 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2624 [(set (ResTy QPR:$Vd),
2625 (ResTy (ShOp (ResTy QPR:$Vn),
2635 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2637 [(set (ResTy QPR:$Vd),
2638 (ResTy (ShOp (ResTy QPR:$Vn),
2704 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2706 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2717 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr, Dt,
2718 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2726 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vn, QPR:$Vm),
2728 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vn),
2729 (OpTy QPR:$Vm))))]> {
2737 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2739 [(set (ResTy QPR:$Vd),
2740 (ResTy (IntOp (ResTy QPR:$Vn),
2749 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2751 [(set (ResTy QPR:$Vd),
2752 (ResTy (IntOp (ResTy QPR:$Vn),
2761 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2763 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2809 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2811 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2812 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2817 (outs QPR:$Vd),
2818 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2821 [(set (ResTy QPR:$Vd),
2822 (ResTy (ShOp (ResTy QPR:$src1),
2823 (ResTy (MulOp QPR:$Vn,
2831 (outs QPR:$Vd),
2832 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2835 [(set (ResTy QPR:$Vd),
2836 (ResTy (ShOp (ResTy QPR:$src1),
2837 (ResTy (MulOp QPR:$Vn,
2854 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2856 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2857 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2873 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2875 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2876 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2883 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2885 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2891 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2892 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2895 [(set QPR:$Vd,
2896 (OpNode (TyQ QPR:$src1),
2903 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2904 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2907 [(set QPR:$Vd,
2908 (OpNode (TyQ QPR:$src1),
2919 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2921 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2931 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2933 [(set QPR:$Vd,
2934 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2939 (outs QPR:$Vd),
2940 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2943 [(set (ResTy QPR:$Vd),
2944 (ResTy (IntOp (ResTy QPR:$src1),
2952 (outs QPR:$Vd),
2953 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2956 [(set (ResTy QPR:$Vd),
2957 (ResTy (IntOp (ResTy QPR:$src1),
2967 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2969 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2978 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2980 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2988 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2990 [(set QPR:$Vd,
2997 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2999 [(set QPR:$Vd,
3009 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3011 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
3022 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3024 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3034 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3036 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
3046 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
3047 [(set QPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
3053 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3055 [(set (ResTy QPR:$Vd),
3063 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3065 [(set (ResTy QPR:$Vd),
3075 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
3077 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
3096 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
3097 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3098 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
3116 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
3118 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
3134 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
3136 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
3145 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
3147 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm), ImmTy:$SIMM)))]>;
3155 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
3157 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
3174 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3175 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3177 [(set QPR:$Vd, (Ty (add QPR:$src1,
3178 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
3194 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3195 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
3197 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
3213 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3215 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
3256 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3258 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
3260 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3262 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
3264 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3266 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
3268 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3270 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
4143 def : Pat<(v8i8 (trunc (NEONvshru (add (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4144 (VADDHNv8i8 QPR:$Vn, QPR:$Vm)>;
4145 def : Pat<(v4i16 (trunc (NEONvshru (add (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4146 (VADDHNv4i16 QPR:$Vn, QPR:$Vm)>;
4147 def : Pat<(v2i32 (trunc (NEONvshru (add (v2i64 QPR:$Vn), QPR:$Vm), 32))),
4148 (VADDHNv2i32 QPR:$Vn, QPR:$Vm)>;
4168 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
4169 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
4170 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
4171 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4174 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
4175 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
4176 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
4177 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4180 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
4181 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
4182 (v4f32 (VMULslfq (v4f32 QPR:$src1),
4183 (v2f32 (EXTRACT_SUBREG QPR:$src2,
4192 def : Pat<(v4f32 (fmul QPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4193 (VMULslfq QPR:$Rn,
4205 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
4206 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4208 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
4209 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4212 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
4213 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4215 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
4216 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4227 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
4228 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4230 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
4231 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4234 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
4235 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4237 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
4238 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4284 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
4285 (mul (v8i16 QPR:$src2),
4286 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4287 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4288 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4292 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
4293 (mul (v4i32 QPR:$src2),
4294 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4295 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4296 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4300 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
4301 (fmul_su (v4f32 QPR:$src2),
4302 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4303 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
4304 (v4f32 QPR:$src2),
4305 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4337 (v8i16 QPR:$src1),
4338 (v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$Vn),
4339 (v8i16 QPR:$Vm))))),
4340 (v8i16 (VQRDMLAHv8i16 QPR:$src1, QPR:$Vn, QPR:$Vm))>;
4342 (v4i32 QPR:$src1),
4343 (v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$Vn),
4344 (v4i32 QPR:$Vm))))),
4345 (v4i32 (VQRDMLAHv4i32 QPR:$src1, QPR:$Vn, QPR:$Vm))>;
4367 (v8i16 QPR:$src1),
4369 (v8i16 QPR:$src2),
4370 (v8i16 (NEONvduplane (v8i16 QPR:$src3),
4372 (v8i16 (VQRDMLAHslv8i16 (v8i16 QPR:$src1),
4373 (v8i16 QPR:$src2),
4375 QPR:$src3,
4379 (v4i32 QPR:$src1),
4381 (v4i32 QPR:$src2),
4382 (v4i32 (NEONvduplane (v4i32 QPR:$src3),
4384 (v4i32 (VQRDMLAHslv4i32 (v4i32 QPR:$src1),
4385 (v4i32 QPR:$src2),
4387 QPR:$src3,
4407 (v8i16 QPR:$src1),
4408 (v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$Vn),
4409 (v8i16 QPR:$Vm))))),
4410 (v8i16 (VQRDMLSHv8i16 QPR:$src1, QPR:$Vn, QPR:$Vm))>;
4412 (v4i32 QPR:$src1),
4413 (v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$Vn),
4414 (v4i32 QPR:$Vm))))),
4415 (v4i32 (VQRDMLSHv4i32 QPR:$src1, QPR:$Vn, QPR:$Vm))>;
4436 (v8i16 QPR:$src1),
4438 (v8i16 QPR:$src2),
4439 (v8i16 (NEONvduplane (v8i16 QPR:$src3),
4441 (v8i16 (VQRDMLSHslv8i16 (v8i16 QPR:$src1),
4442 (v8i16 QPR:$src2),
4444 QPR:$src3,
4448 (v4i32 QPR:$src1),
4450 (v4i32 QPR:$src2),
4451 (v4i32 (NEONvduplane (v4i32 QPR:$src3),
4453 (v4i32 (VQRDMLSHslv4i32 (v4i32 QPR:$src1),
4454 (v4i32 QPR:$src2),
4456 QPR:$src3,
4465 def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1),
4468 (VQDMLALv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4469 def : Pat<(v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1),
4472 (VQDMLALv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4473 def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1),
4477 (VQDMLALslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4478 def : Pat<(v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1),
4482 (VQDMLALslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4502 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
4503 (mul (v8i16 QPR:$src2),
4504 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4505 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4506 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4510 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
4511 (mul (v4i32 QPR:$src2),
4512 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4513 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4514 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4518 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
4519 (fmul_su (v4f32 QPR:$src2),
4520 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4521 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
4522 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4541 def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1),
4544 (VQDMLSLv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4545 def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1),
4548 (VQDMLSLv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4549 def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1),
4553 (VQDMLSLslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4554 def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1),
4558 (VQDMLSLslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4581 def : Pat<(v4f32 (fma QPR:$Vn, QPR:$Vm, QPR:$src1)),
4582 (VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4587 def : Pat<(v4f32 (fma (fneg QPR:$Vn), QPR:$Vm, QPR:$src1)),
4588 (VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4628 def : Pat<(v8i8 (trunc (NEONvshru (sub (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4629 (VSUBHNv8i8 QPR:$Vn, QPR:$Vm)>;
4630 def : Pat<(v4i16 (trunc (NEONvshru (sub (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4631 (VSUBHNv4i16 QPR:$Vn, QPR:$Vm)>;
4632 def : Pat<(v2i32 (trunc (NEONvshru (sub (v2i64 QPR:$Vn), QPR:$Vm), 32))),
4633 (VSUBHNv2i32 QPR:$Vn, QPR:$Vm)>;
4700 (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4704 (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4709 (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4713 (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4760 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4763 [(set QPR:$Vd,
4764 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4769 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4772 [(set QPR:$Vd,
4773 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4785 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4786 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4788 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
4789 (vnotq QPR:$Vm))))]>;
4811 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4814 [(set QPR:$Vd,
4815 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4820 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4823 [(set QPR:$Vd,
4824 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4834 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
4835 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4837 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
4838 (vnotq QPR:$Vm))))]>;
4851 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
4854 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4865 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
4868 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
4879 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
4881 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
4883 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
4923 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4924 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4927 [(set QPR:$Vd,
4928 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
4930 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 QPR:$src1),
4931 (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))),
4932 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4934 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 QPR:$src1),
4935 (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))),
4936 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4938 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 QPR:$src1),
4939 (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))),
4940 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4942 def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 QPR:$src1),
4943 (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))),
4944 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4946 def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 QPR:$src1),
4947 (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))),
4948 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4951 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
4952 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4953 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
4955 def : Pat<(v2i64 (or (and QPR:$Vn, QPR:$Vd),
4956 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4957 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
4969 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4983 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
5243 def : Pat<(v8i8 (trunc (NEONvshru (v8i16 QPR:$Vn), shr_imm8:$amt))),
5244 (VSHRNv8i8 QPR:$Vn, shr_imm8:$amt)>;
5245 def : Pat<(v4i16 (trunc (NEONvshru (v4i32 QPR:$Vn), shr_imm16:$amt))),
5246 (VSHRNv4i16 QPR:$Vn, shr_imm16:$amt)>;
5247 def : Pat<(v2i32 (trunc (NEONvshru (v2i64 QPR:$Vn), shr_imm32:$amt))),
5248 (VSHRNv2i32 QPR:$Vn, shr_imm32:$amt)>;
5346 def : Pat<(xor (v4i32 (bitconvert (v16i8 (NEONvshrs QPR:$src, (i32 7))))),
5347 (v4i32 (bitconvert (v16i8 (add QPR:$src,
5348 (NEONvshrs QPR:$src, (i32 7))))))),
5349 (VABSv16i8 QPR:$src)>;
5350 def : Pat<(xor (v4i32 (bitconvert (v8i16 (NEONvshrs QPR:$src, (i32 15))))),
5351 (v4i32 (bitconvert (v8i16 (add QPR:$src,
5352 (NEONvshrs QPR:$src, (i32 15))))))),
5353 (VABSv8i16 QPR:$src)>;
5354 def : Pat<(xor (v4i32 (NEONvshrs QPR:$src, (i32 31))),
5355 (v4i32 (add QPR:$src, (NEONvshrs QPR:$src, (i32 31))))),
5356 (VABSv4i32 QPR:$src)>;
5375 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
5377 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
5393 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
5395 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
5400 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
5401 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
5402 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
5433 (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2),
5443 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
5452 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
5455 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
5464 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
5467 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
5478 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
5481 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
5489 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
5492 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
5498 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
5501 [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
5517 (VMOVv16i8 QPR:$Vd, nImmVMOVI16ByteReplicate:$Vm, pred:$p)>;
5519 (VMOVv16i8 QPR:$Vd, nImmVMOVI32ByteReplicate:$Vm, pred:$p)>;
5530 (VMOVv16i8 QPR:$Vd, nImmVMVNI16ByteReplicate:$Vm, pred:$p)>;
5532 (VMOVv16i8 QPR:$Vd, nImmVMVNI32ByteReplicate:$Vm, pred:$p)>;
5547 def VMOVQ0 : ARMPseudoExpand<(outs QPR:$Vd), (ins), 4, IIC_VMOVImm,
5548 [(set QPR:$Vd, (v4i32 NEONimmAllZerosV))],
5549 (VMOVv4i32 QPR:$Vd, 0, (ops 14, zero_reg))>,
5596 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
5597 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5600 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
5601 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5604 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
5605 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5608 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
5609 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5612 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5613 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
5621 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5623 (i32 (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5628 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
5629 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
5631 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
5632 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5633 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
5634 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5668 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
5669 (v16i8 (INSERT_SUBREG QPR:$src1,
5670 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
5674 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
5675 (v8i16 (INSERT_SUBREG QPR:$src1,
5676 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
5680 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
5681 (v4i32 (INSERT_SUBREG QPR:$src1,
5682 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
5690 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
5691 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
5694 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5695 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5696 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5697 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5733 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
5735 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5766 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5768 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
5804 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
5805 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
5808 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
5809 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
5812 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
5813 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
5816 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
5817 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
5919 (VCVTf2sq QPR:$Qd, QPR:$Qm, pred:$p)>;
5921 (VCVTf2uq QPR:$Qd, QPR:$Qm, pred:$p)>;
5923 (VCVTs2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
5925 (VCVTu2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
5948 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
5949 (ins QPR:$Vm), IIC_VMOVQ,
5951 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
5961 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
5971 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
5972 (ins QPR:$Vm), IIC_VMOVQ,
5974 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
5990 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
5991 (ins QPR:$Vm), IIC_VMOVQ,
5993 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
6003 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
6004 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
6034 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
6035 (ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm,
6037 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
6038 (Ty QPR:$Vm), imm:$index)))]> {
6075 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
6076 (v4f32 QPR:$Vm),
6078 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
6195 (!cast<Instruction>(NAME#"Q") QPR:$Qd, QPR:$Qm)>;
6352 def : VFPPat<(f64 (sint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))),
6353 (VSITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6356 def : VFPPat<(f64 (uint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))),
6357 (VUITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6412 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
6413 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
6414 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
6416 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
6418 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
6419 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
6420 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
6421 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
6422 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
6424 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
6426 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
6427 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
6428 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
6429 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
6430 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
6431 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
6432 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
6433 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
6434 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
6435 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
6436 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
6438 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
6440 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
6441 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
6442 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
6444 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
6446 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
6447 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
6448 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
6449 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
6482 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (VREV64q32 QPR:$src)>;
6483 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (VREV64q16 QPR:$src)>;
6484 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (VREV64q8 QPR:$src)>;
6485 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (VREV64q32 QPR:$src)>;
6486 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (VREV64q32 QPR:$src)>;
6487 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (VREV32q16 QPR:$src)>;
6488 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (VREV32q8 QPR:$src)>;
6489 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (VREV64q32 QPR:$src)>;
6490 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (VREV64q16 QPR:$src)>;
6491 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (VREV32q16 QPR:$src)>;
6492 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (VREV16q8 QPR:$src)>;
6493 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (VREV64q16 QPR:$src)>;
6494 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (VREV32q16 QPR:$src)>;
6495 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (VREV64q8 QPR:$src)>;
6496 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (VREV32q8 QPR:$src)>;
6497 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (VREV16q8 QPR:$src)>;
6498 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (VREV64q8 QPR:$src)>;
6499 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (VREV32q8 QPR:$src)>;
6500 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (VREV64q32 QPR:$src)>;
6501 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (VREV32q16 QPR:$src)>;
6502 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (VREV32q8 QPR:$src)>;
6503 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (VREV64q32 QPR:$src)>;
6504 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (VREV64q32 QPR:$src)>;
6505 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (VREV64q16 QPR:$src)>;
6506 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (VREV64q8 QPR:$src)>;
6507 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (VREV64q32 QPR:$src)>;
6803 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6807 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6811 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6815 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6820 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6824 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6828 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6835 (VBICiv8i16 QPR:$Vd, nImmSplatNotI16:$imm, pred:$p)>;
6837 (VBICiv4i32 QPR:$Vd, nImmSplatNotI32:$imm, pred:$p)>;
7679 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
7684 (VMVNq QPR:$Vd, QPR:$Vm, pred:$p)>;
7704 (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7706 (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7708 (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7710 (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7712 (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7714 (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7716 (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7736 (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7738 (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7740 (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7742 (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7744 (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7746 (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7748 (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7754 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>;
7764 (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7766 (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7768 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7774 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7778 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7825 (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;