Lines Matching refs:v8i16
1099 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
1400 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16,
2087 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
2129 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
3259 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3262 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
3293 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3294 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
3308 v8i8, v8i16, OpNode>;
3325 v8i8, v8i16, IntOp>;
3339 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3340 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
3371 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
3373 v8i16, v8i16, OpNode, Commutable>;
3382 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>;
3420 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3422 v8i16, v8i16, IntOp, Commutable>;
3441 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3443 v8i16, v8i16, IntOp>;
3457 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
3458 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
3531 v8i8, v8i16, IntOp, Commutable>;
3547 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
3549 v8i16, v8i8, OpNode, Commutable>;
3571 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
3573 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3613 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
3615 v8i16, v8i8, IntOp, Commutable>;
3622 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3624 v8i16, v8i8, IntOp, ExtOp, Commutable>;
3639 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3641 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3668 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3669 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
3682 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3683 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3707 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3708 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3726 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ16,
3727 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3753 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3754 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3795 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3796 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3803 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3804 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3830 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3831 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3832 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3853 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3854 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3855 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3889 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3890 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3926 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3927 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3965 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3966 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
4005 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
4006 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
4041 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
4042 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
4059 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
4060 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> {
4080 v8i8, v8i16, shr_imm8, OpNode> {
4143 def : Pat<(v8i8 (trunc (NEONvshru (add (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4168 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
4169 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
4170 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
4205 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
4206 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4208 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
4227 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
4228 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4230 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
4250 v8i16, v8i8, int_arm_neon_vmullp, 1>;
4284 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
4285 (mul (v8i16 QPR:$src2),
4286 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4287 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4336 def : Pat<(v8i16 (int_arm_neon_vqadds
4337 (v8i16 QPR:$src1),
4338 (v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$Vn),
4339 (v8i16 QPR:$Vm))))),
4340 (v8i16 (VQRDMLAHv8i16 QPR:$src1, QPR:$Vn, QPR:$Vm))>;
4366 def : Pat<(v8i16 (int_arm_neon_vqadds
4367 (v8i16 QPR:$src1),
4368 (v8i16 (int_arm_neon_vqrdmulh
4369 (v8i16 QPR:$src2),
4370 (v8i16 (NEONvduplane (v8i16 QPR:$src3),
4372 (v8i16 (VQRDMLAHslv8i16 (v8i16 QPR:$src1),
4373 (v8i16 QPR:$src2),
4406 def : Pat<(v8i16 (int_arm_neon_vqsubs
4407 (v8i16 QPR:$src1),
4408 (v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$Vn),
4409 (v8i16 QPR:$Vm))))),
4410 (v8i16 (VQRDMLSHv8i16 QPR:$src1, QPR:$Vn, QPR:$Vm))>;
4435 def : Pat<(v8i16 (int_arm_neon_vqsubs
4436 (v8i16 QPR:$src1),
4437 (v8i16 (int_arm_neon_vqrdmulh
4438 (v8i16 QPR:$src2),
4439 (v8i16 (NEONvduplane (v8i16 QPR:$src3),
4441 (v8i16 (VQRDMLSHslv8i16 (v8i16 QPR:$src1),
4442 (v8i16 QPR:$src2),
4502 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
4503 (mul (v8i16 QPR:$src2),
4504 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4505 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4628 def : Pat<(v8i8 (trunc (NEONvshru (sub (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4764 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4815 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4854 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4934 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 QPR:$src1),
4935 (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))),
5219 v8i16, v8i8, imm8>;
5225 def : Pat<(v8i16 (NEONvshl (zext (v8i8 DPR:$Rn)), (i32 8))),
5231 def : Pat<(v8i16 (NEONvshl (sext (v8i8 DPR:$Rn)), (i32 8))),
5243 def : Pat<(v8i8 (trunc (NEONvshru (v8i16 QPR:$Vn), shr_imm8:$amt))),
5350 def : Pat<(xor (v4i32 (bitconvert (v8i16 (NEONvshrs QPR:$src, (i32 15))))),
5351 (v4i32 (bitconvert (v8i16 (add QPR:$src,
5384 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
5401 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
5467 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
5600 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
5608 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
5674 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
5675 (v8i16 (INSERT_SUBREG QPR:$src1,
5717 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
5718 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
5742 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
5789 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
5808 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
5809 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
5841 def : Pat<(v8i16 (anyext (v8i8 DPR:$Vm))), (VMOVLuv8i16 DPR:$Vm)>;
5959 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
5980 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
6008 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
6063 def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> {
6413 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
6420 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
6426 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
6427 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
6428 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
6429 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
6430 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
6433 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
6440 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
6447 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
6483 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (VREV64q16 QPR:$src)>;
6487 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (VREV32q16 QPR:$src)>;
6490 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (VREV64q16 QPR:$src)>;
6491 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (VREV32q16 QPR:$src)>;
6492 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (VREV16q8 QPR:$src)>;
6493 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (VREV64q16 QPR:$src)>;
6494 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (VREV32q16 QPR:$src)>;
6497 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (VREV16q8 QPR:$src)>;
6501 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (VREV32q16 QPR:$src)>;
6505 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (VREV64q16 QPR:$src)>;
6518 // Pat<(v8i16 (extloadvi8 addrmode6:$addr))
6726 defm : Lengthen_Single<"8", "i16", "8">; // v8i8 -> v8i16