Lines Matching refs:imm5

197 // t_addrmode_is4 := reg + imm5 * 4
209 // t_addrmode_is2 := reg + imm5 * 2
221 // t_addrmode_is1 := reg + imm5
592 // Loads: reg/reg and reg/imm5
604   def i : // reg/imm5
610 // Stores: reg/reg and reg/imm5
621   def i : // reg/imm5
913   T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
915                    "asr", "\t$Rd, $Rm, $imm5",
916                    [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
918   bits<5> imm5;
919   let Inst{10-6} = imm5;
998   T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
1000                    "lsl", "\t$Rd, $Rm, $imm5",
1001                    [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>,
1003   bits<5> imm5;
1004   let Inst{10-6} = imm5;
1016   T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1018                    "lsr", "\t$Rd, $Rm, $imm5",
1019                    [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
1021   bits<5> imm5;
1022   let Inst{10-6} = imm5;