Lines Matching refs:SPR
94 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
96 [(set SPR:$Sd, (load addrmode5:$addr))]> {
108 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
110 [(store SPR:$Sd, addrmode5:$addr)]> {
291 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
293 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
307 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
309 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
323 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
325 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
335 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
337 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
349 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
351 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
361 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
363 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
383 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
385 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
403 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
404 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
414 (outs), (ins SPR:$Sd, SPR:$Sm),
416 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
429 (outs), (ins SPR:$Sd, SPR:$Sm),
448 (outs SPR:$Sd), (ins SPR:$Sm),
450 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
466 (outs), (ins SPR:$Sd),
468 [(arm_cmpfp0 SPR:$Sd)]> {
487 (outs), (ins SPR:$Sd),
500 (outs DPR:$Dd), (ins SPR:$Sm),
502 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
517 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
519 [(set SPR:$Sd, (fround DPR:$Dm))]> {
542 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
546 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
550 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
554 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
559 (outs DPR:$Dd), (ins SPR:$Sm),
571 (outs SPR:$Sd), (ins DPR:$Dm),
586 (outs DPR:$Dd), (ins SPR:$Sm),
598 (outs SPR:$Sd), (ins DPR:$Dm),
612 def : Pat<(fp_to_f16 SPR:$a),
613 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
619 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
622 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
628 (outs SPR:$Sd), (ins SPR:$Sm),
636 (outs SPR:$Sd), (ins SPR:$Sm),
644 (outs SPR:$Sd), (ins DPR:$Dm),
659 (outs SPR:$Sd), (ins DPR:$Dm),
675 def : Pat<(i32 (fp_to_sint (node SPR:$a))),
677 (!cast<Instruction>(NAME#"SS") SPR:$a),
679 def : Pat<(i32 (fp_to_uint (node SPR:$a))),
681 (!cast<Instruction>(NAME#"US") SPR:$a),
707 (outs SPR:$Sd), (ins SPR:$Sm),
709 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
717 (outs SPR:$Sd), (ins SPR:$Sm),
719 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
734 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>,
749 (outs SPR:$Sd), (ins SPR:$Sm),
751 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
765 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>,
783 (outs SPR:$Sd), (ins SPR:$Sm),
785 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
793 (outs SPR:$Sd), (ins SPR:$Sm),
802 (outs GPR:$Rt), (ins SPR:$Sn),
804 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
824 (outs SPR:$Sn), (ins GPR:$Rt),
826 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
874 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
896 // FMDHR: GPR -> SPR
897 // FMDLR: GPR -> SPR
927 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
950 // FMRDH: SPR -> GPR
951 // FMRDL: SPR -> GPR
952 // FMRRS: SPR -> GPR
953 // FMRX: SPR system reg -> GPR
954 // FMSRR: GPR -> SPR
996 (outs DPR:$Dd), (ins SPR:$Sm),
1004 (VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1011 (outs SPR:$Sd),(ins SPR:$Sm),
1022 (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1028 (outs DPR:$Dd), (ins SPR:$Sm),
1036 (VUITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1043 (outs SPR:$Sd), (ins SPR:$Sm),
1054 (VUITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1099 (outs SPR:$Sd), (ins DPR:$Dm),
1114 (outs SPR:$Sd), (ins SPR:$Sm),
1124 def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)),
1125 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
1127 def : VFPNoNEONPat<(store (i32 (fp_to_sint (f32 SPR:$a))), addrmode5:$ptr),
1128 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
1131 (outs SPR:$Sd), (ins DPR:$Dm),
1146 (outs SPR:$Sd), (ins SPR:$Sm),
1156 def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)),
1157 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;
1159 def : VFPNoNEONPat<(store (i32 (fp_to_uint (f32 SPR:$a))), addrmode5:$ptr),
1160 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
1166 (outs SPR:$Sd), (ins DPR:$Dm),
1168 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
1173 (outs SPR:$Sd), (ins SPR:$Sm),
1175 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
1180 (outs SPR:$Sd), (ins DPR:$Dm),
1182 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
1187 (outs SPR:$Sd), (ins SPR:$Sm),
1189 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
1232 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1240 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1248 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1256 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1282 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1290 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1298 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1306 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1344 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1346 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1347 SPR:$Sdin))]>,
1358 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1359 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1371 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1373 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1374 SPR:$Sdin))]>,
1385 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1386 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1398 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1400 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1401 SPR:$Sdin))]>,
1412 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1413 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1425 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1427 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1438 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1439 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1454 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1456 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1457 SPR:$Sdin))]>,
1467 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1468 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1476 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
1477 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1489 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1491 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1492 SPR:$Sdin))]>,
1502 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1503 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1511 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
1512 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1518 def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
1519 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1531 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1533 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1534 SPR:$Sdin))]>,
1544 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1545 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1553 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
1554 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1560 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
1561 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1573 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1575 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1585 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1586 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1595 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
1596 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1602 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
1603 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1609 def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
1610 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1624 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
1626 [(set (f32 SPR:$Sd),
1627 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>,
1745 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
1748 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
1813 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;
1818 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1822 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1827 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
1832 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1834 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1842 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1844 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1846 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1848 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1850 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1852 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1862 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;
1873 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>;