Lines Matching refs:Sm
291 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
292 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
293 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
307 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
308 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
309 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
323 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
324 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
325 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
335 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
336 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
337 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
349 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
350 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
351 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
361 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
362 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
363 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
383 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
384 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),
385 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
414 (outs), (ins SPR:$Sd, SPR:$Sm),
415 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
416 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
429 (outs), (ins SPR:$Sd, SPR:$Sm),
430 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
448 (outs SPR:$Sd), (ins SPR:$Sm),
449 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
450 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
500 (outs DPR:$Dd), (ins SPR:$Sm),
501 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
502 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
505 bits<5> Sm;
508 let Inst{3-0} = Sm{4-1};
509 let Inst{5} = Sm{0};
542 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
543 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
546 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
547 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
550 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
551 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
554 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
555 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
559 (outs DPR:$Dd), (ins SPR:$Sm),
560 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm",
563 bits<5> Sm;
566 let Inst{3-0} = Sm{4-1};
567 let Inst{5} = Sm{0};
586 (outs DPR:$Dd), (ins SPR:$Sm),
587 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm",
590 bits<5> Sm;
593 let Inst{3-0} = Sm{4-1};
594 let Inst{5} = Sm{0};
628 (outs SPR:$Sd), (ins SPR:$Sm),
629 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
636 (outs SPR:$Sd), (ins SPR:$Sm),
637 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
707 (outs SPR:$Sd), (ins SPR:$Sm),
708 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
709 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
717 (outs SPR:$Sd), (ins SPR:$Sm),
718 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm",
719 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
733 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"),
734 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>,
749 (outs SPR:$Sd), (ins SPR:$Sm),
750 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),
751 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
764 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
765 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>,
783 (outs SPR:$Sd), (ins SPR:$Sm),
784 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
785 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
793 (outs SPR:$Sd), (ins SPR:$Sm),
794 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
968 bits<5> Sm;
971 let Inst{3-0} = Sm{4-1};
972 let Inst{5} = Sm{0};
986 bits<5> Sm;
989 let Inst{3-0} = Sm{4-1};
990 let Inst{5} = Sm{0};
996 (outs DPR:$Dd), (ins SPR:$Sm),
997 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
1011 (outs SPR:$Sd),(ins SPR:$Sm),
1012 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
1028 (outs DPR:$Dd), (ins SPR:$Sm),
1029 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
1043 (outs SPR:$Sd), (ins SPR:$Sm),
1044 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
1088 bits<5> Sm;
1091 let Inst{3-0} = Sm{4-1};
1092 let Inst{5} = Sm{0};
1114 (outs SPR:$Sd), (ins SPR:$Sm),
1115 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
1146 (outs SPR:$Sd), (ins SPR:$Sm),
1147 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
1173 (outs SPR:$Sd), (ins SPR:$Sm),
1174 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
1175 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
1187 (outs SPR:$Sd), (ins SPR:$Sm),
1188 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
1189 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
1344 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1345 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
1346 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1371 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1372 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
1373 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1398 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1399 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
1400 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1425 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1426 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
1427 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1454 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1455 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm",
1456 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1476 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
1477 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1489 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1490 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm",
1491 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1511 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
1512 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1518 def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
1519 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1531 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1532 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
1533 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1553 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
1554 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1560 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
1561 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1573 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1574 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
1575 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1595 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
1596 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1602 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
1603 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1609 def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
1610 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1624 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
1627 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>,
1817 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
1818 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1821 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
1822 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1827 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
1861 def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
1862 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;